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Staggered CMOS: A Novel Three-Dimensional Technology

Published online by Cambridge University Press:  21 February 2011

E. W. Maby
Affiliation:
Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology, Cambridge, MA 02139
D. A. Antoniadis
Affiliation:
Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology, Cambridge, MA 02139
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Abstract

We report the fabrication of mutually self-aligned IGFET's in two silicon layers which are separated by a thin dielectric film. The transistors are configured such that the heavily doped source and drain regions of a transistor in one layer also serve as the gate electrodes for transistors in the other layer. One application of this three-dimensional technology is the implementation of a compact four-transistor “staggered” CMOS latch circuit which can be used to form part of a static random-access memory cell.

Type
Research Article
Copyright
Copyright © Materials Research Society 1984

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References

REFERENCES

1. Gibbons, J. F. and Lee, K. F., IEEE Electron Device Lett. EDL–l, 117 (1980).10.1109/EDL.1980.25252Google Scholar
2. Robinson, A. L., Antoniadis, D. A. and Maby, E. W., IEDM Tech. Dig., pp. 530533 (1983).Google Scholar
3. Homma, Y., Nozawa, H. and Harada, S., IEEE Trans. Electron Dev. ED–28, 552 (1981).Google Scholar
4. Horwitz, C. M., IEEE Trans. Electron Dev. ED–28, 1320 (1981).10.1109/T-ED.1981.20608Google Scholar
5. Maby, E. W., Geis, M. W., LeCoz, Y.L., Silversmith, D.J., Mountain, R.W. and Antoniadis, D. A., IEEE Electron Device Lett. EDL–2, 241 (1981).Google Scholar
6. Magee, C. W., unpublished.Google Scholar