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Semiconductor Nanocrystal Floating-gate Memory Devices

Published online by Cambridge University Press:  01 February 2011

P. Dimitrakis  and
P. Normand
P. Dimitrakis
Affiliation:
Institute of Microelectronics, NCSR ‘Demokritos’ 15310. Aghia Paraskevi, Greece
P. Normand
Affiliation:
Institute of Microelectronics, NCSR ‘Demokritos’ 15310. Aghia Paraskevi, Greece
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Abstract

Current research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D5.1
Copyright
Copyright © Materials Research Society 2005

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