Experimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit self-assembly process could be successfully adapted beyond 90nm metal nanocrystal memory technology with satisfactory parametric yield in the nanocrystal number density.

Molecular interface with CMOS is an area indispensable to the enhancement of our understanding of the nano-scale world. We report the integration of fullerenes in CMOS gate stack and demonstrate a functional molecular interface by effecting molecular redox operations through non-volatile charge injection in an EEPROM-type device. The gate stack of the MOS capacitor consists of a tunneling thermal oxide. A sub-monolayer of fullerenes is deposited. Then the control oxide is deposited and finally the gate metal is patterned. Charge injection occurs at a specific potential of the fullerene molecules with respect to the conduction band of Si at the Si/SiO2 interface, independent of the concentration of the fullerene sub-monolayer. This strongly indicates molecular redox in solid state that is electrostatically controllable. Such molecular interfaces can be used to enhance the spatial sensitivity of chemical sensors like the CνMOS to be able to interface with macromolecular systems.

Current research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells.

Thin-film uniform metal-ferroelectric-metal (M/F/M) structure between back-to-back Schottky barriers (SBs) is considered. The ferroelectric is assumed to be a p-type semiconductor, and the film thickness is far less than the depletion layer induced by the S.B. Numerical integration of the Poisson equation is used to analyze the influence of double Shottky barriers on the distributions of the electric field, potential, and polarization across the film thickness as functions of external bias and the film electrical history. The range of structure parameters is determined, where the Poisson equation for M/F/M structure can be solved analytically providing an obvious and easy-to-interpret representation of the M/F/M behavior. Electric fields induced by back-to-back SBs under zero external bias compensate each other to a great extent. As a result, the potential across the ferroelectric film remains virtually unchanged providing the flat-band condition in the energy diagram of zero-biased M/F/M structure; in fact, the external bias applied to M/F/M structure exerts influence only on the reverse-biased barrier.

A systematic study on the Si dot formation after chemical vapor deposition on silicon oxide substrates is presented. The process has been followed from the early stages of the dot formation up to 25% of coverages. Structural characterization has been performed by means of energy filtered transmission electron microscopy, which allowed us to observe dot sizes down to 0.5 nm in radius. The nanodots are shown to be surrounded by a depleted zone, where no new Si dots are observed to nucleate. This has been attributed to the adatoms capture mechanism by pre-existing dots, during the deposition. The dot radius and the capture size are shown to collapse onto the same curve, thus indicating the scaling behavior of the process. The adatom diffusion process is shown to restrict the number of nucleation sites, the final dot size and the dot position, thus driving the process toward partial self-order.

In this paper, we describe an all organic molecular memory device that combines the advantages of molecular and organic electronics. We accomplish this by combining C60 molecules with poly(4-vinylphenol) (PVP) and co-dissolving them in iso-propanol. The current-voltage measurements show a large hysteresis in the blend devices, in contrast to pure PVP devices. The thin blend films have been thoroughly characterized using Raman spectroscopy, atomic force microscopy and scanning electron microscopy.

Conventional nonvolatile memories such as Flash and EEPROM memory have successfully evolved toward high density and low cost. Especially, the market and density of flash memories has grown rapidly which leads semiconductor technology. However, there have been concerns about whether this successful progress can be maintained in the future nano era and can satisfy the requirement of diversified future IT market. Flash memories have the advantage of high density with small cell size and by contraries the disadvantage of slow writing speed and limited endurance. This slow writing speed and limited endurance is not aligned with the trend of high speed and reliability for future semiconductor memories.

The future for these conventional nonvolatile memories forces many research groups and companies to develop alternative memories with ideal memory characteristics such as non-volatility, high density, high speed, and low power, which none of the conventional memories can satisfy at the same time.

In this article, I will evaluate the characteristics of future nonvolatile memories such as ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM) and phase change random access memory (PRAM). These memories have been recently evaluated because of the possibility that they can overcome the challenges that conventional memories are facing. Finally we will review critical technology barriers in developing future memory and predict the promising technology to overcome the barriers in conventional and emerging new memories, which will be technology guidelines for future memory development.

A mechanism of the long-time data retention in the p-channel MFIS FETs with Pt/SBT/HfO2/Si gate structures was proposed. The MFIS FETs used in this study exhibited the drain current on/off ratio of approximately 6×103 even after 30 days had elapsed at room temperature. From the leakage current characteristics of the MFIS diode, the bulk leakage current density lower than 10-12 A/cm2 was presumed for 30-days data retention. On the other hand, we showed that the decrease of on-state drain current in the retention characteristics was explained by the flat-band voltage shift of approximately -0.3V for 30 days toward negative voltage direction. Therefore, it was also found that the trapped charge density as low as 1011 cm-2 was needed for obtaining the data retention of 30 days.

Backside storage memories present an alternative to the conventional front-floating gate geometries by storing charge in defects on the back of a thin depleted silicon channel. This paper focuses on the fabrication of these devices using a modified Smart-Cut™ substrate preparation process followed by standard CMOS processing. The substrate is a complex silicon-on-insulator (SOI) substrate where instead of the buried oxide alone a charge trapping multi-layer stack of oxide-nitride-oxide (ONO) is used as the buried insulator. We demonstrate here the operation of these device structures at ultra-short length scales and summarize the characteristics of their operation.

The growth temperature and properties of Ge4Sb3Te3 thin films are presented in this paper. The critical growth temperature of Ge4Sb3Te3 is between 300 and 340 °C. The Ge4Sb3Te3 films can only be grown on a substrate below the critical growth temperature. The typical resistivity and carrier density are in the order of 10-4 Ωcm and 1021 cm-3 for crystalline phase. It has a rock salt crystal structure with a lattice constant of 0.602 nm. Ge4Sb3Te3 has a better thermal stability but a lower crystallization speed than Ge2Sb2Te5.

In this study, we successfully produced PbZr0.4Ti0.6O3 (PZT (40/60)) thin films with high crystallinity and high remnant polarization (Pr) at low process temperatures using pulsed excimer (XeCl) laser irradiation. In our experiments, amorphous PZT films were prepared on Pt/Ti/SiO2/Si substrates by a sol-gel method. A two-step process was used to crystallize the amorphous thin films: the films were annealed at 550°C for 10 min to initiate the nucleation of the PZT perovskite phase, and then annealed with an excimer laser heating at 400°C in a 120 Torr nitrogen gas atmosphere. Laser energy density was varied from 150 to 750 mJ/cm2 per pulse. x-ray diffraction (XRD) patterns show that 150–200 mJ/cm2 range multi-shot excimer laser irradiation drastically improved the crystallinity of the PZT perovskite phase, and FESEM photographs show that the PZT thin film has uniform-sized crystal grains. The ferroelectric properties were found to depend on the laser energy density and shot number. Before the laser annealing, the films show hysteresis loops with low Pr and the loops do not saturate. After laser annealing, the films show highly saturated hysteresis loops, with the Pr increasing from 2.2 μC/cm2 to 23.0 μC/cm2. We also propose a new technology for fabrication of thin film transistor (TFT)-driven FeRAM devices on arbitrary insulator substrate such as on glass.

We report ferroelectric-gate thin film transistors (TFTs) using indium tin oxide (ITO) as a channel material. Bottom-gate structure TFTs have been fabricated using ferroelectric Pb(Zr, Ti)O3 (PZT) film as a gate insulator and ITO channel. Ferroelectric and ITO layers were formed by the sol-gel technique and RF sputtering, respectively. Drain current-drain voltage (ID-VD) characteristics of PZT/ITO ferroelectric-gate TFTs exhibit typical n-channel transistor operations with clear current saturation and electrical properties were improved by the post annealing. Drain current-gate voltage (ID-VG) characteristics demonstrate clear counterclockwise hysteresis loop due to the ferroelectric gate insulator. The obtained memory window is 2 V. The on/off current ratio of more than 102 has been obtained, which indicates that the ITO channel is sufficiently depleted by the ferroelectric polarization.

Influences of the B-site substitution using Dy3+ ion on the crystal structure and ferroelectric properties of lead zirconate titanate (PZT) films were investigated. Dy3+-substituted PZT films with nominal chemical compositions of Pb1.00Dyx (Zr0.40Ti0.60)1-(3x/4)O3 (x = 0 ∼ 0.06) were fabricated by a chemical solution deposition (CSD). Polycrystalline PZT films with preferential orientation of (111)PZT were obtained on (111)Pt/TiO2/SiO2/(100)Si substrates, while epitaxially-grown (111)PZT films were fabricated on (111)SrRuO3//(111)Pt//(100)YSZ//(100)Si substrate. Ratio of PZT lattice parameters (c/a), which corresponds to its crystal anisotropy, was enhanced by the Dy3+-substitution with x = 0.02. Spontaneous polarization (Ps) of Dy3+-substituted PZT film (x = 0.02) along polar [001] axis of PZT lattice was estimated from saturation polarization (Psat) value of the epitaxially-grown (111)PZT film on (111)SrRuO3//(111)Pt//(100)YSZ//(100)Si to be 84 μC/cm2 that was significantly larger than that of non-substituted PZT (= 71 μC/cm2). We concluded that the enhancement of Ps value could be achieved by the Dy3+-substitution that promoted the crystal anisotropy of PZT lattice.

A novel technique termed UV-assisted RTP has been developed and found to offer improvement in material properties, in particular when applied to thin films. Regarding crystallization of SBT, a number of UV-RTP strategies were developed and evaluated. It was demonstrated that UV irradiation of the sample material at a temperature in excess of the MOCVD deposition temperature was found to produce a significant increase in Pr.

The recent advent of nitride-based localized charge-trapping storage has raised much interest in the lateral characterization of the trapped charge distribution, which is fundamental in defining scalability and retention properties. A direct characterization technique based on amplitude-sweep charge-pumping measurements is exploited here to investigate the lateral distribution of trapped electrons along the channel length. Further, the technique is applied to monitor the charge redistribution in time at high temperature.

The effect of annealing in diluted oxygen on the structural characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by ultra-low energy ion implantation (1 keV) is reported. The nanocrystal characteristics (size, density, coverage) have been measured by spatially resolved Electron Energy Loss Spectroscopy using the spectrum-imaging mode of a Scanning Transmission Electron Microscope. Their evolution has been studied as a function of the annealing duration under N2+O2 at 900°C. An extended spherical Deal-Grove model for the self-limiting oxidation of embedded silicon nanocrystals has been carried out. It shows that stress effects, due to the deformation of the oxide, slows down the chemical oxidation rate and leads to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results.

Nanocrystal memories are widely invoked as potential solutions to overcome the scaling limitations of conventional FLASH memories beyond the 80nm technology node. In this study, the deposition of uniform silicon nanocrystals has been developed and optimized in a commercially available vertical furnace, an A400 from ASM.

It has been shown that low pressure chemical vapor deposition (LPCVD) of nanocrystals is feasible in a batch reactor but with a bad size dispersion of the silicon nanocrystals. To improve the size dispersion of the nanocrystals, a novel 2-step process with silane was introduced. In the conventional 1-step process, the oxide surface is exposed to silane at the same partial pressure and temperature during both nucleation and growth of the silicon nanocrystals. In this novel 2-step process, the surface is first exposed briefly to silane at a higher temperature (580–600°C) and following that, the temperature is lowered to allow selective growth on the existing silicon nuclei over the oxide surface. With such an approach, the nucleation step can be separated from the growth step and consequently the size dispersion can be improved by 50%.

Process simulation are performed in order to simulate the full fabrication process of an alternative nano-flash memory in order to optimise it and to improve the understanding of the dot storage formation. The influence of various parameters (oxidation temperature, nanowire shape) have been investigated.

We studied the Nb doping effect on the electrical characteristics of MOCVD-PZT capacitors using uniformly Nb-doped Pb(Zr, Ti)O3 (UND-PZT) and δ-Nb-doped PZT (DND-PZT) prepared by MOCVD. The 2Pr for UND-PZT was small and the UND-PZT hysteresis shifted in a positive direction. However, the 2Pr for DND-PZT decreased by only 5.5% and the hysteresis of DND-PZT didn't shift. In addition, the leakage current of DND-PZT decreased by one order at low bias compared to non-doped PZT, because the δ-Nb-doping layer maintains the barrier height, higher than that of none-doped PZT due to defect compensation. As a result, Nb1% DND-PZT was well suited to use Nb doping which decreases leakage current at low voltage and maintains 2Pr.

Ferroelectric vinylidene fluoride (VDF) molecular films were fabricated by simple vacuum evaporation method, and the ferroelectric properties and its fatigue were investigated. Formation of ferroelectric phase in VDF oligomer with low molecular weight is favored at low substrate temperature around -150°C. The well-ordered VDF oligomer thin films exhibit a lager value of remanent polarization(130mC/m2) than that of Poly(VDF). Fatigues of polarization reversal can be performed over 10∧5 cycles. The VDF oligomer films can be one of candidates for disposable nonvolatile memory with unique features such as flexible, wide areas and low cost processing.