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Self-Aligned Gate Metallization Processes with Low-Thermal Budget

Published online by Cambridge University Press:  10 February 2011

X. W. Lin  and
M. Weling
X. W. Lin
Affiliation:
VLSI Technology, Inc. 1109 McKay Drive, San Jose, CA 95131
M. Weling
Affiliation:
VLSI Technology, Inc. 1109 McKay Drive, San Jose, CA 95131
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Abstract

A novel concept for CMOS transistor gate metallization is described. It is featured with Gate Cloisonné, a process consisting of dielectric deposition over frontend transistors, followed by chemical mechanical polishing to re-expose the gate pattern on a planar dielectric background. Based on this concept, two metallization schemes have been developed. One is self-aligned metal gate process, which allows for low thermal budget gate metallization with element metals such as W and Al, resulting in a very low sheet resistance (< 1 Ω/sq). The other scheme is dual self-aligned silicidation, which enables decoupling of gate silicidation from that of source/drain silicon areas. Titanium based silicidation process is implemented to form thick silicide on narrow polysilicon gates and thin one over active silicon areas. Low gate sheet resistance (≈ 1.9Ω/sq) is achieved with complete suppression of linewidth effects. Both the metallization schemes are a priori scaleable to deep submicron technologies and suitable to fabricating ultra-shallow junction devices with very low gate sheet resistance. Both of them have been implemented in a 0.25-μm CMOS technology.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 514: Symposium I – Advanced Interconnects & Contact Materials & Processes for… , 1998 , 485
Copyright
Copyright © Materials Research Society 1998

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