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Reduction of Threshold Voltage Shift by Bias Annealing of Hydrogenated Amorphous Silicon Thin Film Transistors

Published online by Cambridge University Press:  21 February 2011

S. C. Deane ,
W. I. Milne  and
M. J. Powell
S. C. Deane
Affiliation:
Cambridge University Engineering Department, Cambridge, CB2 1PZ, UK.
W. I. Milne
Affiliation:
Cambridge University Engineering Department, Cambridge, CB2 1PZ, UK.
M. J. Powell
Affiliation:
Philips Research Laboratories, Redhill, Surrey, RH1 5HA, UK.
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Abstract

We show that bias annealing modifies the rate of threshold voltage shift under bias stress in the regime where state creation dominates. Previously we have shown that the deep state distribution near the interface of a-Si:H TFTs can be altered by bias annealing. In particular the energy position of the defects can be made high or low in the energy gap, consistent with the defect pool model.

In this paper, we relate the kinetics of new state creation at room temperature to a particular equilibrated defect distribution. In particular we show that the rate of state creation can be reduced by prior bias annealing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 219: Symposium A – Amorphous Silicon Technology - 1991 , 1991 , 333
Copyright
Copyright © Materials Research Society 1991

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References

REFERENCES

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