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Process Design & Integration of Salicide and Source/Drain Process Modules for Improved Device Performance

Published online by Cambridge University Press:  10 February 2011

Pushkar P. Apte
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243. apte@spdc.ti.com
Sharad Saxena
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Suraj Rao
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Karthik Vasanth
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Douglas A. Prinslow
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Jorge A. Kittl
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Terence Breedijk
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
Gordon Pollack
Affiliation:
Texas Instruments, M/S 3704, 13570 N. Central Expwy, Dallas, TX 75243
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Abstract

In integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

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