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Observation of a Non-stoichiometric Layer at the Silicon Dioxide – Silicon Carbide Interface: Effect of Oxidation Temperature and Post-Oxidation Processing Conditions

Published online by Cambridge University Press:  21 March 2011

K. C. Chang ,
Q. Wahab  and
L. M. Porter
K. C. Chang
Affiliation:
Carnegie Mellon University, Department of Materials Science and Engineering, Pittsburgh, PA 15232, U.S.A.
Q. Wahab
Affiliation:
Linköping University, Department of Physics, S-581 83 Linköping, Sweden.
L. M. Porter
Affiliation:
Carnegie Mellon University, Department of Materials Science and Engineering, Pittsburgh, PA 15232, U.S.A.
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Abstract

Thermal oxides were grown on n-type 6H-SiC(0001) at 1100 °C for 2 hrs in a wet oxygen ambient after the substrates were cleaned using the complete RCA cleaning process. Metal-oxide-semiconductor (MOS) diodes were then fabricated and subsequently cleaned under different annealing conditions, including re-oxidation-, NO-, and forming gas (10% H2 + 90% N2)-annealing at 950 °C for one hour. Measurements of the interface state densities (Dit) at room temperature showed that post oxidation annealing (POA) reduced the Dit values to a varying degree depending on the specific annealing condition. Annealing in NO and forming gas resulted in the largest reduction in Dit values.

Oxides were grown at 950, 1100, and 1250 °C for varying amounts of time without receiving POA. A non-stoichiometric (SixC, x>1) transition layer adjacent to the SiO2/SiC interface has been observed by electron energy loss spectroscopy (EELS). The thickness of this layer was found to increase with oxidation temperature and was not observed at all for a thin oxide grown at 950 °C. The Dit values (close to the conduction band) for diodes with oxides grown at 950°C without POA were lower than the Dit values for the samples oxidized at 1100 °C with any of the POA treatments. While the thickness of the transition layer was found to be dependent on temperature, our results indicate that it is independent of oxide thickness. This transition layer may be associated with the high Dit values and low channel mobilities for SiC MOSFETs.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 640: Symposium H – Silicon Carbide-Materials, Processing, and Devices , 2000 , H5.45
Copyright
Copyright © Materials Research Society 2001

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References

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