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A Nanodamascene Process to be used as a Building Block for Nanodevices

Published online by Cambridge University Press:  01 February 2011

Christian Dubuc ,
Jacques Beauvais  and
Dominique Drouin
Christian Dubuc
Affiliation:
dubuc@emt.inrs.ca, University of Sherbrooke, Electrical engineering, 2500 boul. de l'Universite, Sherbrooke, J1K 2R1, Canada, 450-929-8267
Jacques Beauvais
Affiliation:
jacques.beauvais@usherbrooke.ca, University of Sherbrooke, Department of Electrical Engineering, 2500 boul. de l'Universite, Sherbrooke, Quebec, J1K 2R1, Canada
Dominique Drouin
Affiliation:
dominique.drouin@usherbrooke.ca, University of Sherbrooke, Department of Electrical Engineering, 2500 boul. de l'Universite, Sherbrooke, Quebec, J1K 2R1, Canada
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Abstract

We report a single-electron transistor concept and its related process enabling the fabrication of ultrasmall junction capacitance. The method utilizes a nanodamascene approach where trenches in silicon oxide are covered with a filling material and planarized with chemical mechanical polishing. Single-electron transistors fabricated with this approach were characterized up to 433 K and demonstrated that the nanodamascene process has high resolution, is relatively simple and is highly scalable.

Keywords

lithography (removal)CMPdevices
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 961: Symposium O – Nanostructured and Patterned Materials for Information Storage , 2006 , 0961-O10-07
Copyright
Copyright © Materials Research Society 2007

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References

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