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Mo/Cr Metallization for Silicon Device Interconnection

Published online by Cambridge University Press:  28 February 2011

M. J. Kim  and
R. A. Saia
M. J. Kim
Affiliation:
B. Gorowitz General Electric Company Corporate Research and Development Schenectady, NY 12301
R. A. Saia
Affiliation:
B. Gorowitz General Electric Company Corporate Research and Development Schenectady, NY 12301
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Abstract

A molybdenum and chromium double layer contact has been developed for the first level metallization of VLSI circuits. An 800Å layer of chromium deposited under a thick molybdenum conductor provides good ohmic contact to p+ and n+ silicon and also promotes metal adhesion to the substrate. The molybdenum has good step coverage and acceptable current carrying capacity when its thickness exceeds 5000Å. Both metals are sequentially sputtered in one pumpdown and patterned with a single RIE step using CCI4 + O2. One pm diameter contacts and 1.5µm wide lines are formed in VLSI geometries using all dry etch processes. Electrical characteristics and thermal reliability were evaluated as a function of annealing temperature. Contact resistance and shallow device junctions are stable up to 500°C for p+/n diodes and up to 450°C for n+/p diodes. The sheet resistance of the film in contact with silicon rapidly increases at 525°C as silicon outdiffuses to form (Mox Crr−x)Si2 The mechanism and cause of the high temperature degradation was studied by mean of SIMS, x-ray diffraction analysis, SEM and electrical measurements.

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 71: Symposium F – Materials Issues in Silicon Integrated Circuit Processing , 1986 , 325
Copyright
Copyright © Materials Research Society 1986

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