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Mechanism of a New Post CMP Cleaning for Trench Isolation Process

Published online by Cambridge University Press:  10 February 2011

N. Miyashita
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
Y. Mase
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
J. Takayasu
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
Y. Minami
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
M. Kodera
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
M. Abe
Affiliation:
Microelectronics Center, Toshiba Corporation 8, Shinsugita-cho, Isogo-ku, Yokohama 235–8522, Kanagawa Japan
T. Izumi
Affiliation:
Department of electronics, Tokai Univ. 1117 kitakaname, hiratsuka, Kanagawa, JAPAN
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Abstract

CMP has been revealed as an attractive technique to poly Si of trench planalizing process. Major issues of process integration for that purpose have been post-CMP cleaning process. A new post CMP cleaning process which employed special organic surfactant has been reported in this paper. In general, wafers after CMP process are contaminated by particles and metallic impurities in the case of conventional cleaning method. The contamination introduce the defects into the wafers after oxidation. The contamination was removed by new cleaning method. using DI water containing special organic surfactant and silica particles. The experimental work has focused on critical problems that had to be solved, using AFM, EDX and VPDICP/MS.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

[1]J Steigerwald, M., JGutmann, R., Murarka, S. P.: “Electrochemical Effect in the Chemical Mechanical Polishing of Copper and Titanium Thin Film Used For Multilevel Interconnect Schemes”, Proc. of IEEE-VMIC (1993) p.205 Google Scholar
[2] Sivaram, S., Bath, H., Leggett, R., aury, A. M, Monnig, K., R. Tolles:“Planarizing Interlevel Dielectrics by Chemical Mechanical Polishing”, SOLD STATE TECHNOLOGY (1992.5) p.87 Google Scholar
[3] Poon, S., Sitaram, A. R., Fiordalice, B., Woo, M., Prinz, E., King, C., Gelatos, Perera, A., urnett, D.B, Hoffman, M.: “Integration of Dielectric Chemical Mechanical Polishing Technology Advanced Circuits with Multilayer Interconnects”, Proc. of IEEE-VMIC (1993) p.59 Google Scholar
[4] Ong, W., Robles, S., Sohn, S., Nguyen, B. C.: “Characterization of Inter-metal and Pre-metal Dielectric Oxides for Chemical Mechanical Polishing Process Integration”, Proc. of IEEEVMIC (1993) p.197 Google Scholar
[5] Abbas, S. A.: “Silicon on poly silicon with deep dielectric isolation”, Proc. of IBM’ Technical Disclosure Bulletin Vol. No.7 Dec. 1997 p.2754 Google Scholar
[6] Hetherington, D. L.: “The effects of double-sided scrubbing on removal of particles and metal contamination from chemical-mechanical-polished wafers”, Proc. of DUMIC Conference 1995 ISMIC-101D/95/0156Google Scholar
[7] Miyashita, N., Minami, Y., Katakabe, I., Takayasu, J., Abe, M., Izumi, T.: “Characterization of new post CMP cleaning method for trench isolation process” Proc. of Proceedings of 14th International Vacuum Congress. (1999)P. 71 Google Scholar
[8] Sirtl, E. and Adler, A.: Zeits.fur Metallk.,52 (1961) p.529 Google Scholar