Reported calculations of the diffusion coefficient of silicon self interstitials vary over several orders of magnitude at temperatures of interest for integrated circuit fabrication. In this work, we measure the enhanced diffusion of phosphorus buried layers while interstitials are injected at a wafer surface via thermal oxidation. The starting substrates were either float-zone silicon or Czochralski silicon with a pre-treatment to precipitate excess oxygen. The samples were prepared by implantation of phosphorus followed by the growth of a 40-60µm epitaxial layer. They were then etched anisotropically from the frontside or backside to yield membrane structures. Local oxidation was performed at 1100°C on either the frontside or backside of each wafer and buried layer diffusion was monitored, yielding information about interstitial diffusion in silicon and it’s dependence on bulk properties.