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Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics

Published online by Cambridge University Press:  28 February 2011

William G. Hawkins
William G. Hawkins*
Affiliation:
Xerox Webster Research Center, Webster, New York 14580
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Abstract

A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial Work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into SiO2 occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 53 , 1985 , 429
Copyright
Copyright © Materials Research Society 1986

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References

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