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Low Temperature Epitaxy Of Si/Si1-xGex/Si Multilayers By Low Pressure Rtcvd For Very Thin Soi Applications

Published online by Cambridge University Press:  10 February 2011

D.W. McNeill ,
D.L. Gay ,
X. Lip ,
B.M. Armstrong  and
H.S. Gamble
D.W. McNeill
Affiliation:
Northern Ireland Semiconductor Research Centre, Dept. Electrical and Electronic Engineering, The Queen's University of Belfast, Belfast, BT9 5AH, N.Ireland, U.K.
D.L. Gay
Affiliation:
Now with BCO Technologies Ltd., Glen Road, Belfast.
X. Lip
Affiliation:
Now with Applied Materials, Newbridge, Midlothian, Scotland.
B.M. Armstrong
Affiliation:
Northern Ireland Semiconductor Research Centre, Dept. Electrical and Electronic Engineering, The Queen's University of Belfast, Belfast, BT9 5AH, N.Ireland, U.K.
H.S. Gamble
Affiliation:
Northern Ireland Semiconductor Research Centre, Dept. Electrical and Electronic Engineering, The Queen's University of Belfast, Belfast, BT9 5AH, N.Ireland, U.K.
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Abstract

The growth by rapid thermal chemical vapour deposition of Si/Si1-xGex/Si multilayer structures, suitable for thin bond and etch-back silicon-on-insulator fabrication has been investigated. Surface topography was studied by scanning probe microscopy, and layer contamination by secondary ion mass spectrometry. Smooth layers are only achieved at high growth temperatures (>700°C), and when surface oxide contamination is reduced by a combination of ex-situ HF vapour treatment and in-situ high temperature H2 bake. A surface peak-to-peak roughness of 15nm for a Si/Si1-xGex/Si multilayer structure has been achieved by reducing the growth time at 700°C or less. Further improvement is possible, especially if carbon contamination can be reduced.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 533: Symposium FF – Epitaxy & Applications of Si-Based Heterostructures , 1998 , 307
Copyright
Copyright © Materials Research Society 1998

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