With the continued rapid development of integrated circuits and the evolution towards higher chip component densities brought about by down–scaling of device dimensions, it is useful to assess the limits of performance of presently known device structures using current fabrication technology. The silicon gate field effect transistor is of obvious importance, since at the present limit of decreasing dimensions these devices are expected to give comparable speed and lower powerdelay products than their bipolar counterparts. The rapid developments in fabrication methods such as increases in wafer dimensions coupled with the reduction in device dimensions has led to a reduction in maximum processing temperatures. In particular, this downward trend is incompatible with the necessity to lower contact resistance given appropriate device down–scaling.

In this paper we present techniques using ion implantation and tailored impurity profiles that are compatible with low temperature ohmic contact formation. The application of these techniques to mono- and polycrystalline silicon are presented. Our results suggest that these techniques show considerable promise for semiconductor device applications. As a consequence, a production technology that optimizes the contact resistance to both gate-poly and drain and source regions is being investigated and current results will be presented.