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Laser–Assisted Mos/Sos Transistor Fabrication*

Published online by Cambridge University Press:  15 February 2011

L.D. Hess ,
S.A. Kokorowski ,
G.L. Olson ,
Y.M. Chi ,
A. Gupta  and
J.B. Valdez
L.D. Hess
Affiliation:
Hughes Research Laboratories, Malibu, California, USA
S.A. Kokorowski
Affiliation:
Hughes Research Laboratories, Malibu, California, USA
G.L. Olson
Affiliation:
Hughes Research Laboratories, Malibu, California, USA
Y.M. Chi
Affiliation:
Newport Beach Research Center, Hughes Aircraft Company, Newport Beach, California, USA
A. Gupta
Affiliation:
Newport Beach Research Center, Hughes Aircraft Company, Newport Beach, California, USA
J.B. Valdez
Affiliation:
Newport Beach Research Center, Hughes Aircraft Company, Newport Beach, California, USA
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Abstract

CW laser annealing techniques were incorporated into standard MOS/SOS transistor fabrication procedures and found to be advantageous as compared to conventional furnace methods for electrical activation of ion–implanted source/drain dopants for both N- and P–MOS transistors. Static electrical characteristics of 2.4 μm channel–length transistors are similar for both types of annealing, whereas the speed of devices with cw laser annealed source–drain regions is increased 10 to 40%, depending on the operating voltage.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 4: Symposium A – Laser and Electron-Beam Interactions with Solids , 1981 , 633
Copyright
Copyright © Materials Research Society 1982

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Footnotes

*

Supported in part by U.S. Army ERADCOM, Contract No. DAAK20–80–C–0269.

References

REFERENCES

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5a Yaron, G., Hess, L.D. and Olson, G.L., ibid, pp. 626–631.Google Scholar