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Investigations of Silicon Nano-crystal Floating Gate Memories

Published online by Cambridge University Press:  17 March 2011

Arvind Kumar
Affiliation:
IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A
Jeffrey J. Welser
Affiliation:
IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A
Sandip Tiwari
Affiliation:
School of Electrical Engineering, Cornell University, Ithaca, NY 14853
Farhan Rana
Affiliation:
Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA 02139
Kevin K. Chan
Affiliation:
IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A
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Abstract

As memory continues to be scaled to ever smaller dimensions, the floating-gate memory transistor, which offers a single-element storage cell, becomes more attractive. Typically, this structure has been reserved for nonvolatile applications, where the comparatively high voltages, slow write speeds, and limited cyclability could be tolerated. However, if the floating-gate, which is usually a continuous film of polysilicon, is replaced with a discontinuous film of small floating islands (nano-crystals), a new set of tradeoffs in these performance factors becomes possible, opening the door to broader applications. If these islands are further reduced to the point where Coulomb charging or energy quantization effects become relevant, it is possible to control the charge on the islands at a single (or few) electron level, which offers very low power operation and may enable new functionality. This paper will discuss design and fabrication of these memories, experimental results on fabricated devices, and modeling of what could ultimately be achieved, as well as what limitations will ultimately be reached.

Type
Research Article
Copyright
Copyright © Materials Research Society 2001

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