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Influence of Interface States on Output Characteristics of 4H-SiC MESFETs on Semi–Insulating Substrates

Published online by Cambridge University Press:  21 March 2011

Nabil Sghaier
Affiliation:
Laboratoire de Physique de la Matière (UMR CNRS 5511), Institut National des Sciences Appliquées de Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne cedex, FRANCE.
Abdel K. Souifi
Affiliation:
Laboratoire de Physique de la Matière (UMR CNRS 5511), Institut National des Sciences Appliquées de Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne cedex, FRANCE.
Jean-Marie Bluet
Affiliation:
Laboratoire de Physique de la Matière (UMR CNRS 5511), Institut National des Sciences Appliquées de Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne cedex, FRANCE.
Manuel Berenguer
Affiliation:
Laboratoire de Physique de la Matière (UMR CNRS 5511), Institut National des Sciences Appliquées de Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne cedex, FRANCE.
Gérard Guillot
Affiliation:
Laboratoire de Physique de la Matière (UMR CNRS 5511), Institut National des Sciences Appliquées de Lyon, 20 avenue Albert Einstein, 69621 Villeurbanne cedex, FRANCE.
Olivier Noblanc
Affiliation:
Thomson-CSF/LCR, Domaine de Corbeville, F-91404 Orsay cedex, France.
Christian Brylinski
Affiliation:
Thomson-CSF/LCR, Domaine de Corbeville, F-91404 Orsay cedex, France.
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Abstract

The aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

Type
Research Article
Copyright
Copyright © Materials Research Society 2001

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References

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