Hostname: page-component-848d4c4894-8bljj Total loading time: 0 Render date: 2024-06-22T12:57:41.462Z Has data issue: false hasContentIssue false

Identification and Characterization of Submicron Defects for Semiconductor Processing

Published online by Cambridge University Press:  01 February 2011

Wei Liu
Affiliation:
Physical Analysis Laboratory of Advanced Products Research and Development Laboratory
Aime Fausz
Affiliation:
MOS12 Die Fab
John Svoboda
Affiliation:
MOS12 Die Fab
Brian Butcher
Affiliation:
MRAM, Technology Solutions Organization, Freescale Semiconductor, Inc. Chandler, AZ85224, U.S.A
Rick Williams
Affiliation:
MRAM, Technology Solutions Organization, Freescale Semiconductor, Inc. Chandler, AZ85224, U.S.A
Steve Schauer
Affiliation:
Physical Analysis Laboratory of Advanced Products Research and Development Laboratory
Get access

Abstract

Auger Electron Spectroscopy (AES) is one of the few techniques that has surface sensitivity and small analysis volume to make it the ideal analytical technique for the compositional characterization of submicron defects. However, the integration of defect inspections at only a few processing steps during device fabrication results in the detection of many buried defects. In order to identify these defects, it is necessary to determine their composition. Combined with Focused Ion Beam (FIB) technique to expose the cross section of the buried defect, Auger analysis provides accurate identification of buried defects that are critical for quickly ramping to higher yields and recovering from yield excursions. This paper reports two examples of the use of AES combined with FIB to diagnose processing problems.

Type
Research Article
Copyright
Copyright © Materials Research Society 2005

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Childs, K.D., Naurm, D., and LaVanier, L.A. etc. J. Vac. Sci. Technol. A 14, 2392 (1996)Google Scholar
2 Childs, K.D.; Paul, D.F.; Schauer, S.N. AIP Conference Proceedings 550, 312(2001)Google Scholar
3 Wolf, S., Silicon Processing for the Vlsi Era - Vol. 3 (Lattice Press, Sunset Beach, CA, 1995), P373 Google Scholar
4 Tehrani, S., Chen, E., Durlam, M., DeHerrera, M., Slaughter, J. M., Shi, J., and Kerszykowski, G., J. Appl. Phys. 85, 5822 (1999).Google Scholar
5 Durlam, Mark, Naji, Peter J., Omair, Asim, DeHerrera, Mark, Calder, John, Slaughter, Jon M., Engel, Brad N., Rizzo, Nicholas D., Grynkewich, Greg, Butcher, Brian, Tracy, Clarence, Smith, Ken, Kyler, Kelly W., Ren, J. Jack, Molla, Jaynal A., Feil, William A., Williams, Rick G., and Tehrani, Saied, IEEE J. Solid-State Circuits, 38, 769 (2003)Google Scholar