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Evidence For Heterojunction Effects in Polycrystalline Si1-xGex Thin Film Transistors With Si Caps

Published online by Cambridge University Press:  10 February 2011

Albert W. Wang  and
Krishna C. Saraswat
Albert W. Wang
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
Krishna C. Saraswat
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
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Abstract

Polycrystalline silicon-germanium (poly-Si1-xGex) thin film transistors (TFTs) werefabricated with and without Si interlayers (caps) to buffer the SiO2 gate dielectric and theSi1-xGex channel. Both low temperature processes (≤ 550 °C) compatible with glass for flat panel displays and high temperature processes were used. NMOS TFTs show dramatic performanceimprovements up to moderate (5 to 10 nm) interlayer thicknesses. In contrast, PMOS TFTs showonly small improvements at low interlayer thicknesses (< 5 nm), after which performancedeclines. Computer simulations using an effective medium model for polycrystalline materialssuggest that in addition to interface improvement, a pseudomorphic heterojunction is formedfrom the strained Si cap and unstrained poly-Si1-xGex channel with both conduction and valenceband offsets. These offsets play a significant role in inversion layer formation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 533: Symposium FF – Epitaxy & Applications of Si-Based Heterostructures , 1998 , 145
Copyright
Copyright © Materials Research Society 1998

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References

1. King, T.-J. and Saraswat, K.C., IEEE Trans. Electron Devices 41, 1581 (1994).Google Scholar
2. Neugroschel, A., Margalit, S., and Bar-Lev, A., J. Physics D 6, 1606 (1973).Google Scholar
3. Turan, R. and Finstad, T.G., Semicon. Sci. Tech. 7, 75 (1992).Google Scholar
4. Caragianis, C., Shigesato, Y., and Paine, D.C, J. Electronic Mat. 23, 883 (1994).Google Scholar
5. Iyer, S.S., Solomon, P.M., Kesan, V.P., Bright, A.A., Freeouf, J.L., Nguyen, T.N., and Warren, A.C., IEEE Electron Device Lett. 12, 246 (1991).Google Scholar
6. Tang, A.J., Tsai, J.A., Reif, R., and King, T.-J., Int'l Electron Devices Mtg., 513 (1995).Google Scholar
7. Verdonckt-Vandebroek, S., Crabbé, E.F., Meyerson, B.S., Harame, D.L., Restle, P.J., Stork, J.M.C., Megdanis, A.C., Stanis, C.L., Bright, A.A., Kroesen, G.M.W., and Warren, A.C., IEEE Electron Device Lett. 12, 447 (1991).Google Scholar
8. Garone, P.M., Venkataraman, V., and Sturm, J.C., IEEE Electron Device Lett. 13, 56 ( 1992).Google Scholar
9. Welser, J., Hoyt, J.L., and Gibbons, J.F., Int'l Electron Devices Mtg., 1000 (1992).Google Scholar
10. Wu, I.-W., Chiang, A., Fuse, M., Oveqoglu, L., and Huang, T.Y., J. Appl. Phys. 65, 4036 (1989).Google Scholar
11. Hack, M., Shaw, J.G., LeComber, P.G., and Willums, M., Jap. J. Appl. Phys. 29, L2360 (1990).Google Scholar