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Dopant Segregation at Polycrystalline Silicon Grain Boundaries in Device Fabrication Processes

Published online by Cambridge University Press:  21 February 2011

M. Itoh
Affiliation:
Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan
I. Aikawa
Affiliation:
Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan
N. Hirashita
Affiliation:
Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan
T. Ajioka
Affiliation:
Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan
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Abstract

The dopant segregation at the polycrystalline silicon grain boundaries in device fabrication processes has been studied with a new approach using spreading resistance(SR) measurement, SIMS and cross-sectional TEM(XTEM). Phosphorus implanted LPCVD poly-Si films were annealed at 900°C-1000°C in N2 for 30min. Electrically active dopant concentrations obtained from SR measurements are constant in depth within the poly-Si films. On the other hand, the phosphorus concentration measured by SIMS is found to increase with increasing depth and to have linear relationships to reciprocal grain sizes observed by XTEM for all poly-Si films. The linear relationship indicates that the number of segregated phosphorus atoms per unit grain surface area at the grain boundaries is uniform throughout poly-Si films. Both phosphorus concentrations in the grains and at the grain boundaries are evaluated. The heat of segregation of 1.7eV is obtained from the annealing temperature dependence of the segregation ratio. Our results indicate that carrier concentration in the poly-Si film is more sensitive to annealing temperature in device fabrication processes. The carries concentration is determined by kinetics rather than by equilibrium segregation of dopants.

Type
Research Article
Copyright
Copyright © Materials Research Society 1990

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