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Development of New High-Mounting Density Packages

Published online by Cambridge University Press:  10 February 2011

J. Kasai ,
K. Tsuji  and
Y. Yoneda
J. Kasai
Affiliation:
LSI Packaging Division, Fujitsu Limited, Kawasaki, JAPAN 211–88, kasai@pkga.ed.fujitsu.co.jp
K. Tsuji
Affiliation:
LSI Packaging Division, Fujitsu Limited, Kawasaki, JAPAN 211–88, kasai@pkga.ed.fujitsu.co.jp
Y. Yoneda
Affiliation:
LSI Packaging Division, Fujitsu Limited, Kawasaki, JAPAN 211–88, kasai@pkga.ed.fujitsu.co.jp
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Abstract

In low pin-count packages mounted with a device for portable electronics equipment, we have developed the CSP(Chip Size Package), which guarantees the reliability similar to the former SSOP (Shrink Small Outline Package) despite its drastic miniaturization in size than SSOP. The BCC (Bump Chip Carrier) we developed this time, as the name suggests, is a package with bumps, having the following structure: resin bumps covered with metal film are laid out in the base peripherally as mounted terminals. This resin bump can be formed by molding monolithically with resin sealing, and the connection between the bump and metal film has been implemented using lead frame manufacturing technology and etching technology we have developed. In this paper, we outline the structure and manufacturing technology of BCC as well as the results of reliability evaluation for BCC.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 445: Electronic Packaging Materials Science IX , 1996 , 63
Copyright
Copyright © Materials Research Society 1997

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References

1 Yoneda, Y. et al. : TECHNICAL REPORT OF IEICE ICD95–199 (1995–12).Google Scholar
2 Kasai, J.: “Structure and Application Development of Leadframe Type CSP” INTERNEPCON JAPAN'96 (1996).Google Scholar
3 Kasai, J.: “Development and Micro BGA and QFN by Leadframe Terminal Division Method” First Pan Pacifie Micro Electronics Symposium (1996).Google Scholar
4 Kasai, J.: “LOW COST CHIP SIZE PACKAGE SOLUTIONS FOR ASIC AND MEMOLY APPLICATION” SEMICON EUROPA'96, SEMI TECHNICAL PROGRAM, March 27, 1996.Google Scholar
5 Tsuji, K.: “Development of Leadframe Type CSP by Terminal Formation Etching Method” JPCA SHOW 96 Institute of Circuit Technology Seminar Text, pp 17–24 (1996).Google Scholar
6 Fujita, K.: Nikkei Electronics 1996.8.19 (no.668), pp139–145.Google Scholar
7 Yoneda, Y.: 6th SHM WORKSHOP no. 18 (1996).Google Scholar