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Copper Electroplating for Damascene ULSI Interconnects

Published online by Cambridge University Press:  10 February 2011

S. Lopatin
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088-3453
S. Chen
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088-3453
R. Cheung
Affiliation:
Advanced Micro Devices, Sunnyvale, CA 94088-3453
C. Ryu
Affiliation:
Stanford University, Center for Integrated Systems, Stanford, CA 94305
S. S. Wong
Affiliation:
Stanford University, Center for Integrated Systems, Stanford, CA 94305
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Abstract

Copper was electroplated on sputtered Cu seed layer with Ta diffusion barrier. We achieved enhanced Cu deposition at the bottom of trenches/vias and defect-free filling sub-0.5 μm trenches (down to 0.25 μm width) of high aspect ratio (up to 4:1). Large grains occupying the entire trench were observed. Bottom step coverage of electroplated copper in sub-0.5 μm trenches was estimated to be about 140%, while sidewalls step coverage was about 120%. Via resistance for sub-0.5 μm vias was measured to be below 0.55 Ω. Strong <111> texture, large grains, and low tensile stress were observed in electroplated Cu films and in-laid Cu lines after low temperature anneal.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

1) Dubin, V. M., Chen, S., Cheung, R., Iacoponi, J. and Ting, C.H., “Copper electroplating for ULSI metallizationSemiconductor World, Vol.16, 192 (1997)Google Scholar
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