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The Benefits of Process Parameter Ramping During The Plasma Etching of High Aspect Ratio Silicon Structures

Published online by Cambridge University Press:  10 February 2011

J. Hopkins
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
H. Ashraf
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
J. K. Bhardwaj
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
A. M. Hynes
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
I. Johnston
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
J. N. Shepherd
Affiliation:
Surface Technology Systems Ltd, Imperial Park. Newport, NPI 9UJ, UK.
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Abstract

In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, (ASETM). process satisfies the demanding requirements of the industry. Typically, highly anisotropic. high aspect ratios profiles with fine CD (critical dimension) control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 10μm/min are demonstrated. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASETM process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often-conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

Type
Research Article
Copyright
Copyright © Materials Research Society 1999

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References

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