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WID Rnit Variation Improvements for HSS STI CMP Process using Modified Scribe Lane Pattern Design

Published online by Cambridge University Press:  15 March 2011

Hyuk Kwon
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
Yong-Soo Choi
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
Sang-Hwa Lee
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
Geun-Min Choi
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
Yong-Wook Song
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
Gyu-Han Yoon
Affiliation:
Memory Research & Development Division, Hynix Semiconductor Inc., Ichon-si, Kyunggi-do, South Korea
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Abstract

In the scribe lane, which is located at the frame neighboring two chips, most of the test patterns for monitoring electrical characteristics of memory device as well as various key patterns for photo process are formed. The pattern density of these regions is lower than that of the main chip area, and cause nitride erosion by dishing phenomena during HSS STI CMP process. Nitride erosion occurred in the scribe lane region, could the affect erosion properties of cell region in main chip area, results in within die remain nitride variation and marginal fail in device operation. In this work, in order to prevent these problems, pattern design in the scribe lane was modified so as not to occurs within die remain nitride variation. The effects of improvement in within die remain nitride variation were investigated by FIB-TEM analysis and its correlation with electrical properties were explained.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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