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Using Wafer-Scale Patterns for CMP Analysis

Published online by Cambridge University Press:  14 March 2011

Brian Lee
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Terence Gan
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Duane S. Boning
Affiliation:
Massachusetts Institute of Technology, Cambridge MA
Jeffrey David
Affiliation:
Applied Materials, Santa Clara, CA
Benjamin A. Bonner
Affiliation:
Applied Materials, Santa Clara, CA
Peter McKeever
Affiliation:
Applied Materials, Santa Clara, CA
Thomas H. Osterheld
Affiliation:
Applied Materials, Santa Clara, CA
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Abstract

A new set of wafer-scale patterns has been designed for analysis and modeling of key CMP effects. In particular, the goal of this work is to develop methods to characterize the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means to pattern large trenches (e.g. 1 to 15 mm wide and 15 mm tall) or circles across 4” and 8” wafers, and present oxide polish results using both stacked and solo pads in conventional polish processes. We find that large separation (15 mm) between trenches enables cleaner measurement and analysis. Examination of oxide removal in the center of the trench as a function of trench width shows a saturation at a length comparable to the planarization length extracted from earlier studies of small-scale oxide patterns. Increase in polish pressure is observed to decrease this saturation point. Such wafer scale patterns may provide information on pad flexing limits in addition to planarization length, and promise to be useful in both patterned wafer CMP modeling and studies of wafer scale CMP dependencies such as nanotopography.

Type
Research Article
Copyright
Copyright © Materials Research Society 2000

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References

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