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Ultimately Low Schottky Barrier Height at NiSi/Si Junction by Sulfur Implantation after Silicidation for Aggressive Scaling of MOSFETs
Published online by Cambridge University Press: 31 January 2011
Parasitic resistance, particularly source/drain contact resistance becomes one of the most serious problems to extend MOSFET scaling recently. Nickel silicide (NiSi), with advantages of low resistivity and high scalability, has been chosen as the material for source/drain formation. However, its Schottky barrier height (SBH) of 0.65eV for electrons is so high that it would block electrons from tunneling, therefore becomes an obstacle to further reduce the contact resistance, which is necessary to achieve the future scaling. Among several solutions, high concentration impurity-segregation layers have been introduced at NiSi/Si interfaces to reduce SBH of MS-MOSFETs. Sulfur (S) has been considered to be an efficient material for the segregation-layer to reduce SBH owing to Fermi-level pinning effect. Previous studies have investigated segregation by implanting S before NiSi formation. Because of the high diffusivity of S in Si, S profile becomes broad during silicidation process, which leads to loss of S concentration at the interface. Moreover, S ions spread into the substrate and channel region generate deep impurity levels that induce junction leakage and off leakage, resulting in device performance degradation. In this paper, S implantation after Ni silicidation is proposed to suppress S diffusion because NiSi is expected to be an efficient barrier for S diffusion. In addition, NiSi/Si interface can serve as a potential energetic valley which may trap S during thermal treatment after implantation. In this work, S was implanted into NiSi/n-Si diodes at the energy of 10keV with dose of 5�1014 and 1015 cm-3 after NiSi is formed. The projection range of S in NiSi is about 6nm, while thickness of NiSi is 16nm. Some devices were annealed at 300C and 450C. The I-V characteristics show that SBH is sufficiently reduced as the annealing temperature becomes higher, and it reaches as low as 3.4meV for 450C annealing. SBH of 3.4meV is much lower than the previously reported value of 70meV for which S was implanted before silicidation. The SIMS analysis result also proves the S profile is much sharper than having S-implantation before Ni silicidation, which supports our hypothesis that S diffusion is suppressed through our process and avoid the loss of S concentration at the interface. Moreover, despite the worry that S-implantation might damage the NiSi/Si interface morphology, cross sectional TEM images show that the interfacial flatness is completely the same as that of non-implanted NiSi/Si, indicating that no degradation occurs by S implantation. In summary, S-implantation after NiSi formation, which provides ultimately low SBH at NiSi/Si interface, is a promising technique to realize ultra-low parasitic resistance source/drain for future LSI beyond 16nm generation.
- Research Article
- MRS Online Proceedings Library (OPL) , Volume 1155: Symposium C – CMOS Gate-Stack Scaling–Materials, Interfaces and Reliability Implications , 2009 , 1155-C05-03
- Copyright © Materials Research Society 2009