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Relationships between Interface Structures and Electrical Properties in the High-k/III–V System

Published online by Cambridge University Press:  31 January 2011

Tetsuji Yasuda
Affiliation:
yasuda-t@aist.go.jp
Noriyuki Miyata
Affiliation:
nori.miyata@aist.go.jp, AIST, Tsukuba, Japan
Yuji Urabe
Affiliation:
yuji.urabe@aist.go.jp, AIST, Tsukuba, Japan
Hiroyuki Ishii
Affiliation:
h-ishii@aist.go.jp, AIST, Tsukuba, Japan
Taro Itatani
Affiliation:
t.itatani@aist.go.jp, AIST, Tsukuba, Japan
Hideki Takagi
Affiliation:
takagi.hideki@aist.go.jp, AIST, Tsukuba, Japan
Hisashi Yamada
Affiliation:
yamadah7@sc.sumitomo-chem.co.jp, Sumitomo Chemical, Tsukuba, Japan
Noboru Fukuhara
Affiliation:
fukuharan1@sc.sumitomo-chem.co.jp, Sumitomo Chemical, Tsukuba, Japan
Masahiko Hata
Affiliation:
hatam1@sc.sumitomo-chem.co.jp, Sumitomo Chemical, Tsukuba, Japan
Akihiro Ohtake
Affiliation:
OHTAKE.Akihiro@nims.go.jp, NIMS, Tsukuba, Japan
Masafumi Yokoyama
Affiliation:
yokoyama@mosfet.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Takuya Hoshii
Affiliation:
hoshii@mosfet.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Takashi Haimoto
Affiliation:
haimoto@mosfet.k.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Momoko Deura
Affiliation:
deura@ee.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Masakazu Sugiyama
Affiliation:
sugiyama@ee.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Mitsuru Takenaka
Affiliation:
takenaka@mosfet.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
Shinichi Takagi
Affiliation:
takagi@ee.t.u-tokyo.ac.jp, The University of Tokyo, Tokyo, Japan
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Abstract

Integration of the III–V channel MISFETs on the Si platform is a potential solution to realize performance improvement and power reduction in the sub-22 nm node and beyond. To take advantage of the high electron mobility of III-Vs, the MIS interfaces of high integrity should be developed. This paper reports how the MIS characteristics vary in response to the changes in the interface composition and structures, and discusses the physics and chemistry behind these observations. We fabricated a wide variety of the high-k/III–V interface structures by employing the state-of-the-art technologies of the epitaxial wafers by MOCVD, surface reconstruction control in the MBE environment, wet/dry surface treatments optimized by utilizing XPS/AES analyses, and deposition of quality dielectrics (Al2O3, HfO2) by ALD and EB evaporation. The MIS characteristics were evaluated in the capacitor and FET structures. The talk will include the following topics: the effects of the cation composition (Al, Ga, In) of the III-V bulk on the MIS characteristics [1], the importance of the anion control (N, S) at the interface to improve the MIS characteristics, and the surface orientation ((100) vs. (111)) as a new parameter in the III-V MIS device design [1]. This work was carried out in the Nanoelectronics Project supported by NEDO/METI. [1] T. Yasuda et al., as discussed at 39th IEEE SISC (San Diego, Dec. 2008).

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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