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Post-Anneal Stress Reduction of 200 mm Silicon Wafers in Single Wafer Rapid Thermal Annealing

Published online by Cambridge University Press:  17 March 2011

Tsuyoshi Setokubo
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Eiichi Nakano
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Kazuo Aizawa
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Hidekazu Miyoshi
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Jiro Yamamoto
Affiliation:
Hiroshima Elpida Memory, Inc. 7-10 Yoshikawa Kogyo-Danchi, Higashi Hiroshima, Hiroshima, 739-0198, Japan
Takashi Fukada
Affiliation:
WaferMasters, Inc. 246 East Gish Road, San Jose, CA 95112, U.S.A.
Woo Sik Yoo
Affiliation:
WaferMasters, Inc. 246 East Gish Road, San Jose, CA 95112, U.S.A.
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Abstract

In every wafer processing step wafer stress management is extremely important for advanced device manufacturing. Thermally induced stress on device wafers has a large impact on lithography and affects device yield. Thermally induced stress during rapid thermal annealing (RTA) steps in high density 512MB DRAM device fabrication was investigated using a lamp-based (cold wall) RTA system and compared to results using a furnace-based (hot wall) single wafer RTA system. Compared to the lamp-based (cold wall) system, RTA in a furnace-based (hot wall) system was found to be very effective in suppressing thermally induced stress and increasing device yield due to superior pattern transfer characteristics in lithography.

Type
Research Article
Copyright
Copyright © Materials Research Society 2004

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References

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