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Overview Of Process Integration Issues For Low K Dielectrics

Published online by Cambridge University Press:  10 February 2011

R. H. Havemann
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
M. K. Jain
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
R. S. List
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
A. R. Ralston
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
W-Y. Shih
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
C. Jin
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
M. C. Chang
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
E. M. Zielinski
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
G. A. Dixit
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
A. Singh
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
S. W. Russell
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
J. F. Gaynor
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
A. J. McKerrow
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
W. W. Lee
Affiliation:
Silicon Technology Development, Texas Instruments Inc., Dallas, Texas.
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Abstract

The era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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References

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