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Ion implantation for low-resistive source/drain contacts in FinFET devices

Published online by Cambridge University Press:  01 February 2011

Mark J. H. van Dal
Affiliation:, NXP-TSMC Research Center, Belgium, CMOS Module Integration, Kapeldreef 75, Leuven, 3000, Belgium, +32 16 288612, +32 16 287588
Ray Duffy
Affiliation:, NXP-TSMC Research Center, Kapeldreef 75, Leuven, 3001, Belgium
Bartek J. Pawlak
Affiliation:, NXP-TSMC Research Center, Kapeldreef 75, Leuven, 3001, Belgium
Nadine Collaert
Affiliation:, IMEC, Kapeldreef 75, Leuven, 3001, Belgium
Malgorzata Jurczak
Affiliation:, IMEC, Kapeldreef 75, Leuven, 3001, Belgium
Robert J. P. Lander
Affiliation:, NXP-TSMC Research Center, Kapeldreef 75, Leuven, 3001, Belgium
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FinFET is one of the leading candidates to replace the classical planar MOSFET for future CMOS technologies due to the double-gate configuration of the device leading to an intrinsically superior short channel effect (SCE) control. A major challenge for FinFETs is the increase in parasitic source-drain resistance (Rsd) as the fin width is scaled. As fins must be narrow in order to control SCEs, Rsd reduction is critical. This work will deal with the challenges faced in the use of ion implantation for the low-ohmic source-drain contacts. Firstly a new technique to characterize fin sidewall doping concentration will be introduced. We will have a closer look at the Rsd dependency upon fin width for different fin implant conditions and investigate how the implant conditions affect FinFET device performance. It will be shown that the cause of the device degradation upon fin width scaling is related to the fundamental issues of silicon crystal integrity in thin-body Si after amorphizing implant and recrystallization during source-drain activation.

Research Article
Copyright © Materials Research Society 2008

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