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Effects of Poly-Si Annealing on Gate Oxide Charging Damage in Poly-Si Gate Etching Process

Published online by Cambridge University Press:  01 February 2011

Daniel Chong
Affiliation:
National University of Singapore, Dept of Electrical and Computer Engineering, Silicon Nano Device Laboratory, 10 Kent Ridge Crescent, Singapore 119260
Won Jong Yoo
Affiliation:
National University of Singapore, Dept of Electrical and Computer Engineering, Silicon Nano Device Laboratory, 10 Kent Ridge Crescent, Singapore 119260
Lap Chan
Affiliation:
Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, Street 2, Singapore 738406
Alex See
Affiliation:
Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, Street 2, Singapore 738406
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Abstract

The effects of the poly-Si annealing on gate oxide charging damage in the gate etching process were investigated. Our electrical test results show that gate oxide charging damage can be reduced if the poly-Si is not annealed prior to the gate etching process.

Type
Research Article
Copyright
Copyright © Materials Research Society 2002

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References

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