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3D System Integration Technologies

Published online by Cambridge University Press:  01 February 2011

Peter Ramm ,
Armin Klumpp ,
Reinhard Merkel ,
Josef Weber ,
Robert Wieland ,
Andreas Ostmann  and
Jürgen Wolf
Peter Ramm
Affiliation:
Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germanypeter.ramm@izm-m.fraunhofer.de
Armin Klumpp
Affiliation:
Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germanypeter.ramm@izm-m.fraunhofer.de
Reinhard Merkel
Affiliation:
Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germanypeter.ramm@izm-m.fraunhofer.de
Josef Weber
Affiliation:
Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germanypeter.ramm@izm-m.fraunhofer.de
Robert Wieland
Affiliation:
Fraunhofer Institute for Reliability and Microintegration, Munich Division Hansastrasse 27d, 80686 Munich, Germanypeter.ramm@izm-m.fraunhofer.de
Andreas Ostmann
Affiliation:
Technical University of Berlin Gustav-Meyer-Allee 25, 13355 Berlin, Germany
Jürgen Wolf
Affiliation:
Technical University of Berlin Gustav-Meyer-Allee 25, 13355 Berlin, Germany
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Abstract

In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.

The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 766: Symposium E – Materials, Technology and Reliability for Advanced Interconnects and Low-k Dielectrics - 2003 , 2003 , E5.6
Copyright
Copyright © Materials Research Society 2003

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References

1.International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.netGoogle Scholar
2. Akasaka, Y., Proc. IEEE 74, 1703 (1986).Google Scholar
3. Bertin, C. L., et al., IEEE Trans. on Components, Hybrids and Manufacturing Technology 16(8) 1006 (1993).Google Scholar
4. Barret, J., et al., Proc. IEEE Electronic Components and Technology Conference, 656 (1995).Google Scholar
5. Ostmann, A., Neumann, A., Welser, S., Jung, E., Böttcher, L., and Reichl, H., Proc. Polytronic Conference, 160 (2002).Google Scholar
6. Gann, K. D., HDI Magazine, December issue (1999).Google Scholar
7.www.intel.orgGoogle Scholar
8. Pinel, S., Marty, A., Tasselli, J., Bailbe, J., Beyne, E., Hoof, R. Van, Marco, S., Morante, J., Vendier, O., Huan, M., IEEE Trans. on Components and Packaging Technologies. 25(2) 244 (2002).Google Scholar
9. Hübner, H., Ehrmann, O., Eigner, M., Gruber, W., Klumpp, A., Merkel, R., Ramm, P., Roth, M., Weber, J., Wieland, R., Proc. Advanced Metallization Conference 2002 (AMC 2002), edited by Melnick, B.M., Cale, T.S., Zaima, S., Ohba, T. (Mater. Res. Soc. Proc. V-18, Warrendale).Google Scholar
10. Kurino, H., Nakamura, T., Lee, K.W., Igarashi, Y., Mizokusa, T., Yamada, Y., Morooka, T., and Koyanagi, M., Proc. Advanced Metallization Conference 2001 (AMC 2001), edited by Mckerrow, A.J., Shacham-Diamond, Y., Zaima, S., Ohba, T. (Mater. Res. Soc. Proc. V-17, Warrendale).Google Scholar
11.www.aset.or.jpGoogle Scholar
12. Yonemura, H., Tomisaka, M., Hoshino, M., Takahashi, K., Kadota, H., Proc. Advanced Metallization Conference 2002 (AMC 2002), edited by Melnick, B.M., Cale, T.S., Zaima, S., Ohba, T. (Mater. Res. Soc. Proc. V-18, Warrendale).Google Scholar
13. Ramm, P., Bonfert, D., Gieser, H., Haufe, J., Iberl, F., Klumpp, A., Kux, A., Wieland, R., Proc. International Interconnect Technology Conference 2001 (IITC 2001), 160.Google Scholar
14. Bernstein, L., Bartolomew, H., Trans. Met. Soc. AIME 236, 404 (1966).Google Scholar