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0.1μm Interconnect Technology Challenges and the Sia Roadmap

Published online by Cambridge University Press:  15 February 2011

Tom Seidel ,
Bin Zhao ,
Sematech  and
T X Austin
Tom Seidel
Affiliation:
Now at Genus, Sunnyvale, CA
Bin Zhao
Affiliation:
Now at Rockwell Semiconductor Systems, Newport Beach, CA
Sematech
Affiliation:
Now at Genus, Sunnyvale, CA
T X Austin
Affiliation:
Now at Genus, Sunnyvale, CA
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Abstract

Analysis of the National Technology Roadmap for Semiconductors (SIA) indicates a potential crisis in performance and reliability regarding the scaling of interconnects. In the future, increased component density and performance (e.g. logic instructions / sec.) may not be able to be achieved simultaneously for technology generations well before the manufacture of 0.1μm feature sizes circa 2005. Thermal management and engineering of signal noise are key issues. Although much can be done to achieve higher speed with product design architecture, one must consider new material paradigms by 0. 1μm generation to address the RC crisis.

Needs exist in low cost simplified processes across a broad area of applications: local salicide interconnects, lower process temperature for poly-metal dielectric (to enable shallower junctions), lower dielectric constant materials for interconnects, and robust barriers for interconnect plugs and wiring metals. A shift to lower dielectric constant (low-k) materials (e.g. SiO-F, polymers, or aerogels) will be used as soon as integrated processes are demonstrated and manufacturing tools become available. The next full generation window of opportunity is the 0.18um generation (1GB) scheduled for manufacturing prototyping in 1998.

This paper reviews the overall Roadmap characteristics, major solution strategies, and outlines the challenges in design, technology, and integration for 0.18μm and 0.1μm generations. Topics reviewed include discussion of process architectures and electrical characterization methodologies. Among the most challenging areas we have: control and lowering of contact resistance, manufacturing interconnects at aspect ratios exceeding 4:1, use of very low dielectric constant materials in multilevel counts approaching 6–7, use of controllable ultra thin barrier materials for interconnect plugs and wiring, barriers and cladding for containment and passivation of Cu, development of manufacturing worthy selective processes, engineering stress/electromigration issues and thermal management of low-k dielectric systems. New materials must be introduced into existing technology frameworks while designs migrate to lower voltage operation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 427: Symposium K – Advanced Metallization for Future ULSI , 1996 , 3
Copyright
Copyright © Materials Research Society 1996

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