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Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking

Published online by Cambridge University Press:  07 October 2020

L. Arnaud*
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
C. Karam
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
N. Bresson
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
C. Dubarry
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
S. Borel
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
M. Assous
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
G. Mauguen
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
F. Fournel
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
M. Gottardi
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
T. Mourier
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
S. Cheramy
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
F. Servant
Affiliation:
University Grenoble Alpes, CEA LETI, GrenobleF-38000, France
*
Address all correspondence to L. Arnaud at lucile.arnaud@cea.fr
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Abstract

Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 μm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV) <2 μm to an ultimate thinning as low as 3 μm. Alignment performance was characterized by post-bonding for two superposed hybrid bonding interfaces. In our set of wafers, modeling the alignment with translation, rotation, and scaling components enables us to optimize the residuals down to 3σ < 100 nm. A process flow of thin TSV with a fine pitch of 2 μm for high-density vertical interconnect through a three-wafer stack was developed. Via-last TSV architecture was adopted with 1 μm TSV diameter and 10 μm thickness. Lithography, etching solutions, Ti/TiN barrier deposition, and void-free Cu filling solutions were demonstrated. TSV cross sections after CMP and connections with top and bottom Cu damascene lines show good profile control. Process developments are matured and can be reliably used in the fabrication of an electrical test vehicle including vertical interconnects associating multi-wafers stacking with a hybrid bonding process and high-density thin TSV applicable to low pitches (<5 μm).

Type
Prospective Articles
Copyright
Copyright © The Author(s), 2020, published on behalf of Materials Research Society by Cambridge University Press

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References

Benaissa, L., Di Cioccio, L., Beilliard, Y., Coudrain, P., Dominguez, S., Balan, V., Enot, T., Imbert, B., Millet, L., and Chevobbe, S.Next generation image sensor via direct hybrid bonding. In Proceedings of IEEE 17th Electronics Packaging and Technology Conference (EPTC) (IEEE, Singapore, Singapore, 2015), pp. 13.Google Scholar
Thomas, D., Michailos, J., Rochereau, K.: “Challenges and capabilities of 3D integration in CMOS imaging sensors,” ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), Cracow, Poland, 2019; pp. 54–56.CrossRefGoogle Scholar
Vivet, P., Sicard, G., Millet, L., Chevobbe, S., Ben Chehida, K., Cubero, L.A., Alegre, M., Bouvier, M., Valentian, A., Lepecq, M., Dombek, T., Bichler, O., Thuriès, S., Lattard, D., Cheramy, S., Batude, P., and Clermid, F.: Advanced 3D technologies and architecture for 3D image sensors. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition (IEEE, Florence, Italy, 2019), pp. 674679.CrossRefGoogle Scholar
Kagawa, Y., Fujii, N., Kobayashi, K., Nishi, S., Takeshita, S., Taura, J., Takahashi, H., Nishimura, Y., Tatani, K., Kawamura, M., Nakayama, H., Nagano, T., Ohno, K., Iwamoto, H., Kadomura, S., and Hiramaya, T.: Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding. In Proceedings of 2016 IEEE International Electron Devices Meeting (IEEE, San Francisco, CA, USA, 2016), pp. 208211.Google Scholar
Jourdon, J., Lhostis, S., Moreau, S., Chossat, J., Arnoux, M., Sart, C., Henrion, Y., Lamontagne, P., Arnaud, L., Bresson, N., Balan, V., Euvrard, C., Scevola, D., Deloffre, E., Mermoz, S., Martin, A., Bilgen, H., Andre, F., Charles, C., Bouchu, D., Farcy, A., Guillaumet, S., Jouve, A., Fremont, H., and Cheramy, S.: Hybrid bonding for 3D stacked image sensor: impact of pitch shrinkage on interconnect robustness. In Proceedings of 2018 IEEE International Electron Devices Meeting (IEEE, San Francisco, CA, USA, 2018), pp. 157160.Google Scholar
Millet, L., Chevobbe, S., Andriamisaina, C., Benaiisa, L., Dechaseaux, E., Beigne, E., Ben Chehida, K., Lepecq, M., Darouich, M., Guellec, F., Dombek, T., and Duranton, M.: A 5500FPS 85GOPS/W 3D stacked BSI vision chip based on parallel in-focal-plane acquisition and processing. In IEEE Journal of Solid State Circuits (IEEE, Honolulu, HI, USA, 2019), pp. 10961104.Google Scholar
Lhostis, S., Farcy, A., Deloffre, E., Lorut, F., Le Berrigo, A., Moreau, S., Balan, V., Fournel, F., Mermoz, S., Henrion, Y., Berthier, L., Bailly, F., Jouve, A., Cheramy, S., Scevola, D., Guyader, F., Gigon, F., Besset, C., Pellisier, S., Gay, L., Hotellier, N., Rebhan, B., Arnoux, M., Maier, G.A., and Chitu, L.: Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors. In Proceedings of 2016 IEEE Electronic Components and Technology Conference (IEEE, Las Vegas, NV, USA, 2016), pp. 869876.Google Scholar
Fournel, F., Moriceau, H., Larrey, V., Morales, C., Mauguen, G., Bridoux, C., and Rieutord, F.: From direct bonding mechanism to 3D application. In Proceedings of 2018 IEEE International Interconnect Technology Conference (IEEE, Santa Clara, CA, USA, 2018), pp. 175178.CrossRefGoogle Scholar
Djomeni, L., Mourier, T., Minoret, S., Fadloun, S., Piallat, F., Burges, S., Price, A., Zhou, Y., Jones, C., Mathiot, D., and Maitrejean, S.: Study of low temperature MOCVD deposition of TiN barrier layer for copper diffusion in high aspect ratio through silicon vias. Microelectron. Eng. 120, 127132 (2014).CrossRefGoogle Scholar
Zu, Q., Fang, J., and Chen, L.: A chip scale chemical mechanical planarization model for copper interconnect structures. Microelectron. Eng. 149, 1424 (2016).Google Scholar
Tseng, W.T., Cheng, T.J., Jusang, A., and Baumann, F.: Modulation of within wafer and within die topography for damascene copper in advanced technology. In Proceedings of International Interconnect Technology Conference (IEEE, Santa Clara, CA, USA, 2018), pp. 8284.Google Scholar
Balan, V., Seignard, A., Scevola, D., Lugand, J.F., DiCioccio, L., and Rivoire, M.: CMP process optimization for bonding applications. In Proceedings of 2012 International Conference on Planarization/CMP Technology (VDE, Grenoble, France, 2012), pp. 177183.Google Scholar
Jouve, A., Balan, V., Bresson, N., Euvrard, C., Fournel, F., Exbrayat, Y., Mauguen, G., Abdel Sater, M., Beitia, C., Arnaud, L., Cheramy, S., Farcy, A., Guillaumet, S., and Mermoz, S.: 1 μm pitch direct hybrid bonding with <300 nm wafer to wafer overlay accuracy. In SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, Burlingame, CA, USA, 2017), pp. 12.Google Scholar
Arnaud, L., Moreau, S., Jouve, A., Jani, I., Lattard, D., Fournel, F., Euvrard, C., Exbrayat, Y., Balan, V., Bresson, N., Lhostis, S., Jourdon, J., Deloffre, E., Guillaumet, S., Farcy, A., Gousseau, S., and Arnoux, M.: Fine pitch 3D interconnections with hybrid bonding technology: from process robustness to reliability results. In Proc of IEEE International Reliability Physics Symposium (IEEE, Burlingame, CA, USA, 2018), pp. 4D.4-14D.4-7.Google Scholar
Rebhan, B., Bernauer, M., Wagenleitner, T., Heilig, M., Kurz, F., Lhostis, S., Deloffre, E., Jouve, A., Balan, V., and Chitu, L.: <200 nm Waferto- wafer overlay accuracy in wafer level Cu/SiO hybrid bonding for BSI CIS. In Proceedings of 2015 IEEE Electronics Packaging Technology Conference (IEEE, Singapore, Singapore, 2015), pp. 14.Google Scholar
Coudrain, P., Charbonnier, J., Garnier, A., Vivet, P., Velard, R., Vinci, A., Ponthenier, F., Farcy, A., Segaud, R., Chausse, P., Arnaud, L., Lattard, D., Guthmuller, E., Romano, G., Gueugnot, A., Berger, F., Beltritti, J., Mourier, T., Gottardi, M., Minoret, S., Ribière, C., Romero, G., Philip, P.E., Exbrayet, Y., Scevola, D., Campos, D., Argoud, M., Allouti, N., Ellouet, R., Fuguet Tortolero, C., Aumont, C., Dutoit, D., Legalland, C., Michailos, J., Cheramy, S., and Simon, G.: Active interposer technology for chiplet-based advanced 3D system architectures. In Proceedings of 2019 IEEE Electronic Components and Technology Conference (IEEE, Las Vegas, NV, USA, 2019), pp. 569578.Google Scholar
Kim, S.W., Detalle, M., Peng, L., Nolmans, P., Heylen, N., Velenis, D., Miller, A., Beyer, G., and Beyne, E.: Ultra-fine pitch 3D integration using face to face hybrid wafer bonding combined with a via-middle through-silicon-via process. In Proceedings of IEEE Electronic Components and Technology Conference (IEEE, Las Vegas, NV, USA, 2016), pp. 11791185.Google Scholar
Van Huylenbroeck, S., De Vos, J., El-Mekki, Z., Jamieson, G., Muga, K., Stucchi, M., Miller, A., Beyer, G., and Beyne, E.: A highly reliable 1.4 μm pitch via-last TSV module for wafer-to-wafer hybrid bonded 3D-SOC systems. In Proceedings of 2019 IEEE Electronic Components and Technology Conference (IEEE, Las Vegas, NV, USA, 2019), pp. 10351040.Google Scholar
Gaillard, F., Religieux, L., Mourier, T., Ribière, C., Vandroux, L., Suhr, D., Raynal, F., and Mellec, V.: Electrografted copper seed layer for high aspect ratio TSVs interposer metallization. ECS Trans. 64, 922 (2015).CrossRefGoogle Scholar
Mourier, T., Gottardi, M., Romero, G., Philip, P.E., Verrun, S., Guittet, G., Doussot, C., and Mevellec, V.: Advanced barrier and seed layer deposition enabling multiple type of TSVs integration. In Proceedings of IEEE- IMAPS International Device Packaging Conference (IEEE, Fountain Hills, Arizona, 2019), pp. 16.Google Scholar
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