Over the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

The prospect of utilizing alternative transistor channel materials for ultrahigh performance transistors will require suitable gate dielectrics for surface-channel field-effect devices. With the utilization of deposited gate dielectrics in large-scale production for Si-based integrated circuits by atomic layer deposition, extending this technology to channel materials that exhibit high bulk mobility behavior is of interest. A review of the current status for atomic layer deposited high-κ dielectrics on Ge and III–V channel materials is presented.

The need for high-κ gate dielectrics and metal gates in advanced integrated circuits has reopened the door to Ge and III–V compounds as potential replacements for silicon channels, offering the possibility to further increase the performances of complementary metal oxide semiconductor (CMOS) circuits, as well as adding new functionalities. Yet, a fundamental issue related to high-mobility channels in CMOS circuits is the electrical passivation of their interfaces (i.e., achieving a low density of interface defects) approaching state-of-the-art Si-based devices. Here we discuss promising approaches for the passivation of Ge and III–V compounds and highlight insights obtained by combining experimental characterization techniques with first-principles simulations.

An overview is given on scientific and device advances for InGaAs metal oxide semiconductor heterostructures and inversion channel metal oxide semiconductor field-effect transistors (MOSFETs), with emphasis on results using ultrahigh vacuum-deposited Ga2O3(Gd2O3) [GGO] as high-κ dielectrics. Regardless of the approaches used to deposit high-κ dielectrics on InGaAs, critical material and electrical parameters of fabricating inversion channel InGaAs MOSFETs must be ready for complementary MOS technology beyond the 16-nm node, and some of these parameters have been achieved. These parameters include low interfacial density of states; low electrical leakage currents; high-temperature (800–900°C) thermal stability for high-κ dielectrics/InGaAs heterostructures, where the amorphous oxide structure and atomically smooth and sharp interfaces are retained; and oxide scalability with a capacitance equivalent thickness of ≤1 nm. Interfacial chemical properties and band parameters, which are important for device design in the high κs/InGaAs, have been thoroughly studied. Representative enhancement-mode InGaAs MOSFETs are compared and correlated with the interfacial structures. Deposition methods and electrical characteristics of high-κ dielectrics on InGaA are discussed. The inversion channel InGaAs MOSFETs of 0.4–1.0 μm gate length have exhibited excellent device performance in terms of drain current and transconductance.

The scaling of transistors to smaller dimensions and the exploration of devices with III–V and Ge channels for digital logic places serious demands on the ohmic contacts used in these devices. Contacts with extremely low specific contact resistances are required to take full advantage of the performance promised by alternative semiconductor materials. In addition, device processes and contact morphologies must be compatible with the geometry and feature sizes of the transistors. In this article, we begin by reviewing what is known about contacts to Ge, InGaAs, InAs, and InSb, including the role of Fermi level pinning on the Schottky barrier that is often formed at the metal/semiconductor interface and common strategies for forming ohmic contacts. Then we turn our attention to the additional challenges faced when preparing ohmic contacts for the many types of field-effect transistors now under development for Ge and III–V complementary field-effect transistor technology.

Research in n-channel field-effect transistors based upon III–V compound semiconductors has been very productive over the last 30 years, with successful applications in a variety of high-speed analog circuits. For digital applications, complementary circuits are desirable to minimize static power consumption. Hence, p-channel transistors are also needed. Unfortunately, hole mobilities are generally much lower than electron mobilities for III–V compounds. This article reviews the recent work to enhance hole mobilities in antimonide-based quantum wells. Epitaxial heterostructures have been grown with the channel material in 1–2% compressive strain. The strain modifies the valence band structure, resulting in hole mobilities as high as 1500 cm2/Vs. The next steps toward an ultra-low-power complementary metal oxide semiconductor technology will include development of a compatible insulator technology and integration of n- and p-channel transistors.

Turnbull performed much experimental and theoretical research on nucleation and on fundamental aspects of phase transformations in condensed matter. Nucleation of precipitates followed in parallel or sequentially by their growth and coarsening is a complex scientific subject and technologically highly relevant because of the many critical roles played by structural metallic alloys and their relevance to the energy problem. The focus herein is on nucleation, growth, and coarsening of precipitates employing atom-probe tomography, lattice kinetic Monte Carlo simulations, and diffusion theory, which constitute a unique approach for studying phase separation in concentrated multicomponent alloys.