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Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

Published online by Cambridge University Press:  25 July 2017

Andreas Kerber
Andreas Kerber*
Affiliation:
GLOBALFOUNDRIES Inc., 400 Stone Break Road extension, Malta, NY 12020, USA
*
*(Email: andreas.kerber@globalfoundries.com)
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Abstract

MG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.

In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

Keywords

dielectricdeviceselectrical properties
Type
Articles
Information
MRS Advances , Volume 2 , Issue 52: Electronic Devices and Materials , 2017 , pp. 2973 - 2982
Copyright
Copyright © Materials Research Society 2017 

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References

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