Hostname: page-component-77c89778f8-gvh9x Total loading time: 0 Render date: 2024-07-19T22:08:23.507Z Has data issue: false hasContentIssue false

Dynamics, Design, and Application of a Silicon-on-Insulator Technology Based Neuron

Published online by Cambridge University Press:  08 June 2018

S. Dutta
Affiliation:
Indian Institute of Technology Bombay
T. Chavan
Affiliation:
Indian Institute of Technology Bombay
S. Shukla
Affiliation:
Indian Institute of Technology Bombay
V. Kumar
Affiliation:
Indian Institute of Technology Bombay
A. Shukla
Affiliation:
Indian Institute of Technology Bombay
N. Mohapatra
Affiliation:
Indian Institute of Technology Gandhinagar
U. Ganguly*
Affiliation:
Indian Institute of Technology Bombay
*
Get access

Abstract:

Spiking Neural Networks propose to mimic nature’s way of recognizing patterns and making decisions in a fuzzy manner. To develop such networks in hardware, a highly manufacturable technology is required. We have proposed a silicon-based leaky integrate and fire (LIF) neuron, on a sufficiently matured 32 nm CMOS silicon-on-insulator (SOI) technology. The floating body effect of the partially depleted (PD) SOI transistor is used to store “holes” generated by impact ionization in the floating body, which performs the “integrate” function. Recombination or equivalent hole loss mimics the “leak” functions. The “hole” storage reduces the source barrier to increase the transistor current. Upon reaching a threshold current level, an external circuit records a “firing” event and resets the SOI MOSFET by draining all the stored holes. In terms of application, the neuron is able to show classification problems with reasonable accuracy. We looked at the effect of scaling experimentally. Channel length scaling reduces voltage for impact ionization and enables sharper impact ionization producing significant designability of the neuron. A circuit equivalence is also demonstrated to understand the dynamics qualitatively. Three distinct regimes are observed during integration based on different hole leakage mechanism.

Type
Articles
Copyright
Copyright © Materials Research Society 2018 

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

Indiveri, G., Chicca, E., and Douglas, R., IEEE Trans. Neural Networks 17, 211221 (2006).CrossRefGoogle Scholar
Wijekoon, J. H. B. and Dudek, P., Neural Networks 21, 524534 (2008).CrossRefGoogle Scholar
Joubert, A., Belhadj, B., Temam, O., and Heliot, R., Int. Jt. Conf. Neural Networks, 15 (2012).Google Scholar
Moon, K., Cha, E., Lee, D., Jang, J., Park, J., and Hwang, H., Int. Symp. VLSI Technol. Syst. Appl., 910 (2016).Google Scholar
Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A., and Eleftheriou, E., Nature Nanotechnology 11, 693699 (2016).CrossRefGoogle Scholar
Lashkare, S., Chouhan, S., Chavan, T., Bhat, A., Kumbhare, P., and Ganguly, U., IEEE Electron Device Lett. 39, 484487 (2018).CrossRefGoogle Scholar
Dutta, S., Kumar, V., Shukla, A., Mohapatra, N. R., and Ganguly, U., Sci. Rep. 7, 19 (2017).Google Scholar
Shin, J., Koch, C., IEEE Trans. Neural Networks 10, 12321238 (1999).CrossRefGoogle Scholar
Gupta, A. and Long, L., Int. Jt. Conf. Neural Networks, 10541060 (2009).Google Scholar
Biswas, A., Prasad, S., Lashkare, S., and Ganguly, U., “A simple and efficient SNN and its performance & robustness evaluation method to enable hardware implementation,” arXiv:1612.02233 [cs.NE].Google Scholar
Santurkar, S. and Rajendran, B., Int. Jt. Conf. Neural Networks, 1-8 (2015)Google Scholar