A technique for very thin silicon oxide measurements using energy filtered TEM (EFTEM) is presented and applied for BiCMOS technology optimization.

In advanced VLSI circuits, thin silicon oxide layers are used as critical part of active devices such as MOS or bipolar transistors (BiCMOS). Today the 2 nm thick gate oxides of the 0.12 urn generation MOS transistors can be controlled using high resolution TEM (HRTEM). However, for the next generations these measurements will become difficult or will necessitate Cs corrected microscopes'. For the NPN bipolar transistor very thin oxides (less than 0.5 nm) are used at the base-emitter interface to control the forward base (hole) current and improve the transistor current gain. This interface presents generally some roughness and the oxide control is impossible using HRTEM. in this communication we demonstrate a new technique for very thin oxide measurement using low loss energy filtered TEM (EFTEM).