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The Reduceron reconfigured and re-evaluated

Part of: JFP Research Articles

Published online by Cambridge University Press:  10 July 2012

MATTHEW NAYLOR  and
COLIN RUNCIMAN
MATTHEW NAYLOR
Affiliation:
Department of Computer Science, University of York, York, North Yorkshire, UK (e-mail: mfn@cs.york.ac.uk, colin@cs.york.ac.uk)
COLIN RUNCIMAN
Affiliation:
Department of Computer Science, University of York, York, North Yorkshire, UK (e-mail: mfn@cs.york.ac.uk, colin@cs.york.ac.uk)
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Abstract

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A new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

Type
Articles
Information
Journal of Functional Programming , Volume 22 , Special Issue 4-5: ICFP 2010 , September 2012 , pp. 574 - 613
Copyright
Copyright © Cambridge University Press 2012

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