Book contents
- Frontmatter
- Contents
- Preface
- 1 Introduction
- 2 Design considerations
- 3 Hybrid voltage–current programming
- 4 Enhanced-settling current programming
- 5 Charge-based driving scheme
- 6 High-resolution architectures
- 7 Summary and outlook
- Appendix A Enhanced voltage driving schemes
- Appendix B OLED electrical calibration
- References
- Index
4 - Enhanced-settling current programming
Published online by Cambridge University Press: 05 September 2013
- Frontmatter
- Contents
- Preface
- 1 Introduction
- 2 Design considerations
- 3 Hybrid voltage–current programming
- 4 Enhanced-settling current programming
- 5 Charge-based driving scheme
- 6 High-resolution architectures
- 7 Summary and outlook
- Appendix A Enhanced voltage driving schemes
- Appendix B OLED electrical calibration
- References
- Index
Summary
Although the current mode active matrix provides an intrinsic immunity to mismatches and differential aging, the long settling time at low current levels and large parasitic capacitance is a lingering issue. As explained in Chapter 2, the major source of the settling time in current programming is the large parasitic capacitance. Although using small switch transistors can reduce the parasitic capacitance to some extent [17], the optimized settling time still cannot fit the programming time required for most applications. In addition, the acceleration techniques cannot improve the settling time significantly, particularly if low mobility technologies are used. As a result, driving schemes are required that can reduce the effect of parasitic capacitance based on localized current sources or external driver assistance. This chapter reviews the local current source, current feedback mechanism, and positive feedback described in [98] and [99].
Localized current source
This technique is more useful for compensating for a threshold voltage shift under bias stress and does not work well for process variation. However, it can be used in conjunction with external calibration techniques described in Chapter 6. The idea is to develop the current sources for each pixel locally and therefore eliminate the parasitic capacitance altogether. Our studies show that most TFTs including a-Si:H TFTs are stable if they are under bias stress for a fraction of frame time. Figure 4.1 shows the results of stressing a TFT under 6.5 µA for different stress time during 16 ms frame time. As it can be seen, the output current of the TFT is stable over time even at 500 µs stress time. A local current source based on the short-term stability of the TFTs is demonstrated in Figure 4.2. Here, TLCS converts the voltage stored on its gate to a current. The current in turn adjusts the source voltage of the drive TFT to allow the entire current to pass through the drive TFT. After the programming is finished, the gate voltage of TLCS turns to a reset voltage and so TLCS stays OFF for the rest of the frame time. Figure 4.3 demonstrates the compensation performance of the local current source driving scheme. Here, the threshold voltage of T1 is modified in the simulations and its effect is captured on voltage created at node B and the output current of T1.
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- Chapter
- Information
- Thin Film Transistor Circuits and Systems , pp. 74 - 92Publisher: Cambridge University PressPrint publication year: 2013