This paper details the development of a technique to improve the minority carrier lifetime of 4H-SiC thick (≥ 100 μm) n-type epitaxial layers through multiple thermal oxidations. A steady improvement in lifetime is seen with each oxidation step, improving from a starting ambipolar carrier lifetime of 1.09 µs to 11.2 µs after 4 oxidation steps and a high-temperature anneal. This multiple-oxidation lifetime enhancement technique is compared to a single high-temperature oxidation step, and a carbon implantation followed by a high-temperature anneal, which are traditional ways to achieve high ambipolar lifetime in 4H-SiC n-type epilayers. The multiple oxidation treatment resulted in a high minimum carrier lifetime of 6 µs, compared to < 2 µs for other treatments. The implications of lifetime enhancement to high-voltage/high-current 4H-SiC power devices are also discussed.

TDDB measurements of NMOS capacitor fabricated with 1200°C dry oxide with 1300°C N2O anneal were performed at 175°C and 300°C under high positive bias stress. The devices are biased into strong accumulation mode such that the field in the oxide is high enough to collect breakdown data in a reasonable period of time. We observe that at 175°C, a 100-year Mean Time to Failure (MTTF) is obtained at an electric field of 3 MV/cm in the oxide. The TDDB measurement has also been performed at 300°C where lifetime has been reduced by a few orders of magnitude, but with an acceptable 100-year MTTF. Recent reliability results on similarly oxidized MOSFETs have shown failures along the same trend as the n-type capacitors, indicating that MOSFETs and MOS capacitors can have similar reliability despite inherent processing and structural differences. PMOS capacitors fabricated with the aforementioned dry + N2O process as well as capacitors fabricated using the low DIT nitridation techniques show acceptable MTTF of 100 years at the nominal operating electric field of 3 MV/cm.

Very high critical field, reasonable bulk electron mobility, and high thermal conductivity make 4H-Silicon carbide very attractive for high voltage power devices. These advantages make high performance unipolar switching devices with blocking voltages greater than 1 kV possible in 4H-SiC. Several exploratory devices, such as vertical MOSFETs and JFETs, have been reported in SiC. However, most of the previous works were focused on high voltage aspects of the devices, and the high speed switching aspects of the SiC unipolar devices were largely neglected. In this paper, we report on the static and dynamic characteristics of our 4H-SiC DMOSFETs. A simple model of the on-state characteristics of 4H-SiC DMOSFETs is also presented.

This paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (E C ) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μ eff ) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μ eff . NO anneal, which was reported to be very effective in increasing the μ eff of SiC MOSFETS in p-type epilayers, did not produce reasonable μ eff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μ eff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μ eff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.