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Impact evaluation of DC operating condition on DPD linearizability and power efficiency in GaN-based power amplifiers

  • Konrad Jędrzejewski (a1), Dawid W. Rosołowski (a2) and Wojciech Wojtasiak (a2)

Abstract

The paper presents the results of studies on the effect of transistor DC operating conditions on GaN power amplifiers’ (PAs) power efficiency and linearity improved by digital predistortion (DPD). The single-ended 10 W (ISM2.45 GHz) and 150 W (3.4/3.6 GHz) GaN HEMT PAs excited by wideband LTE20 E-TM1.1 signal were tested. To check the applicability of the small-signal approach for designing of LTE signals’ PAs, the 150 W PA using transistor model extracted from S-parameters measured at the properly selected operating points was designed. The conventional DPD based on the indirect learning architecture and the memory polynomial model of PA non-linearity was implemented. The results of the research show that in case of class A and B PAs operating up to several dozen watts, an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor can be achieved. However, a noticeable ACLR improvement with a coincident increase in power-added efficiency (PAE) can be obtained by choosing the compromise DC operating point and using DPD. In the case of high-PAs, the linearity and efficiency are strongly dependent on the load of a transistor, thus the role of DPD is significantly increased.

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Author for correspondence: Konrad Jędrzejewski, E-mail: konrad.jedrzejewski@pw.edu.pl

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Impact evaluation of DC operating condition on DPD linearizability and power efficiency in GaN-based power amplifiers

  • Konrad Jędrzejewski (a1), Dawid W. Rosołowski (a2) and Wojciech Wojtasiak (a2)

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