This chapter considers the chip rate processing functions that relate to the FDD mode receiver. When addressing specific implementation issues, we focus particularly on the UE aspects and, where reasonable to do so, make comments on the implications for the Node B. The chapter starts with a consideration of the receiver and the ADC - the link between the analogue and the digital domains. We continue with the reference architecture for the UE that was presented in Chapter 5. Following this, we then consider the other major chip rate functions in the receiver, including the rake receiver and the cell acquisition functions.
Analogue to digital converter (ADC)
We start by considering the receiver reference architecture illustrated in Figure 5.44. We consider the chip rate processing functions in the receiver to start at the ADC. For the ADC it is necessary to consider criteria such as the sampling rate and the dynamic range; and there are different considerations for the Node B and the UE. We will also need to consider the location of selectivity filtering within the receiver. Some takes place at the RF/IF, some at the analogue baseband and some at the digital baseband. The amount of digital baseband filtering affects the ADC dynamic range requirements.