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  • Print publication year: 2009
  • Online publication date: June 2012

9 - Current Limitations and Future Challenges


Since 2003, the peak frequency at which single processors and chip multiprocessors have operated has remained largely unchanged. One basic reason is that power dissipation effects have limited frequency increases. In addition, difficulties in extracting more parallelism at the instruction level, design complexity, and the effects of wire lengths have resulted in a performance plateau for single processors. We elaborate on some of these issues in this chapter.

While improvements in clock frequency and in ILP exploitation have been stalled, Moore's law is still valid, and the amount of logic that can be laid out on a chip is still increasing. Adding more cache memory to a single processor to fill all the on-chip real estate has reached a point of diminishing return, performancewise. Multithreaded processors, which mitigate the effects of the memory wall, and multiprocessors on a chip (CMP, also called multicores) are the current approach to attaining more performance. A question that is of primary importance to computer architects and to computer users in general is the structure of future CMPs, as mentioned in the previous chapter.

In a conservative evolutionary fashion, future CMPs might look like those we have presented in Chapter 8, with naturally a slightly larger number of cores. Questions of whether there should be many simple cores vs. fewer high-performance ones, and of whether the cores should be homogeneous or not, have already been touched upon previously. Although speed is still the primary metric, other aspects such as reliability and security have gained importance.

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