Book contents
- Frontmatter
- Contents
- Acknowledgments
- 1 Introduction
- 2 Channel-based asynchronous design
- 3 Modeling channel-based designs
- 4 Pipeline performance
- 5 Performance analysis and optimization
- 6 Deadlock
- 7 A taxonomy of design styles
- 8 Synthesis-based controller design
- 9 Micropipeline design
- 10 Syntax-directed translation
- 11 Quasi-delay-insensitive pipeline templates
- 12 Timed pipeline templates
- 13 Single-track pipeline templates
- 14 Asynchronous crossbar
- 15 Design example: the Fano algorithm
- Index
- References
4 - Pipeline performance
Published online by Cambridge University Press: 26 February 2010
- Frontmatter
- Contents
- Acknowledgments
- 1 Introduction
- 2 Channel-based asynchronous design
- 3 Modeling channel-based designs
- 4 Pipeline performance
- 5 Performance analysis and optimization
- 6 Deadlock
- 7 A taxonomy of design styles
- 8 Synthesis-based controller design
- 9 Micropipeline design
- 10 Syntax-directed translation
- 11 Quasi-delay-insensitive pipeline templates
- 12 Timed pipeline templates
- 13 Single-track pipeline templates
- 14 Asynchronous crossbar
- 15 Design example: the Fano algorithm
- Index
- References
Summary
In the synchronous world, the performance of a pipelined design is straightforward and is characterized by throughput and latency. Throughput is measured in terms of results per second. It is the inverse of the clock frequency for a synchronous system that generates a new result every clock cycle. It can be a multiple of this value if the synchronous system generates multiple results every clock cycle, and it is a fraction of this value if it requires multiple clock cycles between the generation of results. Latency is measured as the number of clock cycles required to generate a result after the associated primary inputs are made available. In pipelined synchronous systems, the latency is a measure of the pipeline depth of the system.
The cycle time in an asynchronous system is the period between two results. Unlike in a synchronous circuit it is not dictated by a clock frequency but rather by the time between successive output tokens. Because this time can vary between tokens, it is often taken to be the average time between output tokens. Since asynchronous systems often have a warm-up period during which there is irregular or no generation of output tokens, the average measured cycle time is typically a long-term average for which the behavior during the warm-up period is insignificant. An asynchronous system's throughput is simply the inverse of its cycle time.
The latency of an asynchronous system is the time between input tokens being consumed at the primary inputs and output tokens being generated.
- Type
- Chapter
- Information
- A Designer's Guide to Asynchronous VLSI , pp. 66 - 83Publisher: Cambridge University PressPrint publication year: 2010