15 - Interconnect considerations
from Section V - Interconnect considerations
Published online by Cambridge University Press: 05 February 2015
Summary
Introduction
The exponential growth of the electronics industry has been guided by the continual reduction in feature size of microchips manufactured using silicon-based CMOS technology. This reduction in feature size, commonly known as dimensional scaling, has enabled significant improvements in transistor performance and power – a higher transistor density for improved functionality, complexity, and performance of microchips; and a reduction in the cost per function. These benefits have enabled the semiconductor industry to offer a wide range of new products at every technology generation.
The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond the 10-year visibility limit. Many logic devices that require innovations in materials, use of heterogeneous technologies, and the exploitation of alternative state variables and non-binary computation schemes are under investigation to extend Moore’s law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc.
Besides smaller and faster transistors, the semiconductor industry requires fast and dense interconnects to manufacture high-performance microchips. The evolution of integrated circuits from an embedded system of only a few components to large-scale systems with billions of devices transformed the interconnection problem into one of the major threats to continue improving the performances of microchips at each new technology node [1]. Interconnects impose major limits on the performance of integrated circuits because of the delay they add to critical paths, the energy they dissipate, the noise and jitter they induce, and the degrading metal and dielectric reliability due to vulnerability to electromigration (EM) and time-dependent dielectric breakdown (TDDB), respectively. All of these limitations worsen with dimensional scaling.
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- CMOS and BeyondLogic Switches for Terascale Integrated Circuits, pp. 381 - 412Publisher: Cambridge University PressPrint publication year: 2015
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