Book contents
- Frontmatter
- Contents
- Preface
- 1 Controlling complexity
- 2 A Verilogical place to start
- 3 Defining the instruction set architecture
- 4 Algorithmic behavioral modeling
- 5 Building an assembler for VeSPA
- 6 Pipelining
- 7 Implementation of the pipelined processor
- 8 Verification
- A The VeSPA instruction set architecture (ISA)
- B The VASM assembler
- Index
- VeSPA Instruction Set
4 - Algorithmic behavioral modeling
Published online by Cambridge University Press: 31 October 2009
- Frontmatter
- Contents
- Preface
- 1 Controlling complexity
- 2 A Verilogical place to start
- 3 Defining the instruction set architecture
- 4 Algorithmic behavioral modeling
- 5 Building an assembler for VeSPA
- 6 Pipelining
- 7 Implementation of the pipelined processor
- 8 Verification
- A The VeSPA instruction set architecture (ISA)
- B The VASM assembler
- Index
- VeSPA Instruction Set
Summary
The sciences do not try to explain, they hardly even try to interpret, they mainly make models. By a model is meant a mathematical construct which, with the addition of certain verbal interpretations, describes observed phenomena. The justification of such a mathematical construct is solely and precisely that it is expected to work.
John Von NeumannIn the previous chapter, we defined the instruction set architecture for the VeSPA processor. This ISA definition includes all of the storage elements that comprise the processor's state and are accessible to the assembly language programmer. It also includes a description of each instruction and how it affects these state elements. Our next step is to develop a simulation model of this ISA to verify that our instruction definitions are complete, that we have included the right mix of instructions, that the state elements we defined are appropriate, and so forth. Our completed simulation model will be capable of executing programs written in the processor's machine language. (In the next chapter, we describe an assembler for generating machine language programs.)
Our goal in this chapter is to develop an algorithmic behavioral model of the VeSPA processor. This type of model describes what each instruction does while ignoring the implementation details needed to actually construct the logic that ultimately will produce this behavior. For example, at this stage, we do not care whether the ALU uses a ripple-carry adder or a carry-lookahead adder. We are concerned only that the ADD instruction causes the sum of two values stored in the register file to be written to the correct destination register. One important consideration is that this behavioral model ignores all timing information.
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- Information
- Designing Digital Computer Systems with Verilog , pp. 58 - 81Publisher: Cambridge University PressPrint publication year: 2004