Heterojunction with intrinsic thin layer (HIT) solar cells have achieved conversion efficiencies higher than 22%. Yet, many questions concerning the device physics governing these cells remain unanswered. We use numerical modeling to analyze the role of a-Si:H layers and tunneling on cell performance. For cells with n-type c-Si (n-HIT cells), incorporating the indium-tin-oxide (ITO) as an n-type semiconductor creates an n+/p/n structure. Most device simulations do not work with this structure. Our modeling indicates that the n+/p/n device often produces irregular S-shaped current density–voltage (J-V) curves, which have been observed experimentally but were not previously understood. However, if tunneling is included, there are specific conditions where the n+/p/n structure performs as a robust solar cell with efficiencies exceeding 20%. Additional analysis examines voltage-dependent carrier collection in n-HIT cells, as well as material and interface properties that limit fill factor. In p-HIT cells, modeling the ITO layer as a semiconductor, rather than as a metallic contact, significantly reduces the impact of a-Si:H layer parameters on device performance. In p-HIT cells, the a-Si:H layers adjacent to the ITO layer play the role of a buffer that reduces interface recombination at the a-Si:H/c-Si interface and prevents tunneling of electrons from the ITO layer to the c-Si absorber. Tunneling through the a-Si:H layers adjacent to the back contact is important to attain regular J-V curves.

Polycrystalline Cd1-xMgxTe (CMT) thin films are a potential absorber material for two-junction thin-film tandem solar cell applications because the desired top cell bandgap range of 1.6 to 1.8 eV is readily obtained using CMT with only small resultant changes in the lattice constant from that of CdTe. Tandem devices require the top cell to have a transparent back contact to transmit the sub-bandgap spectrum to the bottom cell. Sputtered Cu-doped ZnTe (ZnTe:Cu) thin films, which offer potential as a transparent back contact interface layer, have been used successfully in CdTe devices. We apply ZnTe:Cu back contacts to CMT devices to continue development toward a transparent top cell. We describe the effects of depositing ZnTe:Cu at different temperatures and with different Cu contents on the net acceptor concentration, minority carrier lifetime, and device performance. We present here the highest reported CMT device efficiency of 9.6% at a bandgap of 1.57 eV.

Several wet-processing steps are used in fabricating high-efficiency CdTe/CdS solar cells. These steps can hinder in-line processing; thus, developing an all-dry processing option is attractive for a manufacturing-friendly process. In this study, we systematically modified the baseline process used in our laboratory to replace CdS deposited by chemical-bath deposition (CBD) with sputter-deposited CdS and Cu-doped graphite paste back-contact with Cu-doped ZnTe deposited by radio-frequency sputtering. In addition to CdTe deposited by close-spaced sublimation, we also used conventionally evaporated CdTe. The results show that replacing only CBD CdS with oxygenated CdS deposited by sputtering produces devices with performance comparable to baseline devices if the front bilayer SnO2 is replaced by a Cd2SnO4/ZnSnO alloy. Replacing the graphite paste back-contact with sputter-deposited Cu-doped ZnTe resulted in device performance comparable to baseline devices. Incorporating both dry processing steps gave performance comparable to the devices with sputtered CdS with a SnO2 front contact. We used capacitance-voltage and minority-carrier lifetime measurements to analyze the factors affecting device performance and we present the results here.

A set of 24 identically made CdS/CdTe devices were subjected to accelerated lifetime testing (ALT) under open-circuit bias, 1 sun illumination, and temperatures of 60, 80, 100, and 120 °C. A total of 6 identical devices were tested for statistical purposes at each temperature. Current density-voltage (JV) measurements were made on stressed cells for up to 2000+ hours. Device performance parameters were calculated as a function of temperature and stress time using discrete element circuit models. Forward current behavior was represented by two parallel diodes to simulate recombination currents in the quasi-neutral (QNR) and space-charge (SCR) regions. Backcontact behavior was studied using a parallel combination blocking diode and shunt conductance. A systematic pattern of degradation was apparent with increased stress temperature. At 60 °C, degradation associated with the CdTe/backcontact dominates. At temperatures above 80 °C, greater losses in fill factor (FF) and open-circuit voltage (Voc) were observed. Recombination current modeling of JV data attributes this to increased space-charge recombination. Calculated diffusion lengths based upon an Arrhenius-derived activation energy of 0.63 eV in this temperature-range suggests Cu diffusion into the SCR is mechanistically responsible for the observed increased recombination, and decreased Voc and FF. At lower temperatures (60 to 80 ºC), degradation was considerably slower with a measured activation energy of 2.9 eV.

Here we will compare four techniques that are commonly used for diagnosis of the lifetime of photovoltaic materials. The strengths and weaknesses of these techniques will be shown and discussed.

Polycrystalline thin-film CdTe is one of the leading materials used in photovoltaic solar cells. One way to improve device performance and stability is through understanding how various process steps alter defect states in the CdTe layer. Low-temperature photoluminescence (PL) studies show a 1.456-eV PL peak in single-crystal CdTe that is likely due to a Cui-OTe defect complex. A similar peak, observed in as-deposited glass/SnO2:F/CdS/CdTe thin-film structures, strongly suggests a common origin. The 1.456-eV peak is also seen in a thin-film sample after performing the CdCl2 treatment needed for high efficiencies.

The extent to which grain boundaries (GBs) in polycrystalline materials may be detrimental, benign, or even beneficial is explored with numerical simulations in two dimensions. We focus on the effects of GB recombination in Cu(In,Ga)Se2 (CIGS) solar cells and its effects on solar-cell performance. The simulations predict that (1) for device effciency exceeding 17%, the effective GB recombination velocity must be less than 104 cm/s; (2) grain boundaries within the space-charge region (SCR) lower the open-circuit voltage, whereas the short-circuit current is reduced by grain boundaries in the bulk material; and (3) horizontal GBs are relatively benign unless they are located in the SCR. Modifications to the electronic structure near grain boundaries show that charge-induced band-bending at grain boundaries will most likely have a negative effect on device performance, whereas a down-shift in the valence-band energy at the grain surface can effectively passivate the GBs and reduce the effective recombination velocity. For the models considered, GBs generally have a deleterious effect on effciency, and GBs alone can not explain the apparent superiority of polycrystalline over single-crystalline CIGS materials.