We have fabricated a new magnetic field enhanced solid phase crystallization (FESPC) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which shows the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs. The mobility (μ) and threshold voltage (VTH) of p-type TFTs of which the channel width and length are 5 μm and 7 μm, respectively are 31.98 cm2/Vs and -6.14 V, at VDS=-0.1 V. In the FESPC TFTs, the characteristics caused by grain boundary are remarkable due to large number of grain boundaries in the channel compared with poly-Si TFTs. The VTH of the TFT which have 5 μm channel length is smaller than that of 18 μm channel length by 1.36 V, which is considerably large value. It is due to the large number of grain boundaries in the channel and the high lateral electric field. The grain boundary potential barrier height is decreased, when the large lateral electric field is applied (which is called DIGBL effect). As a result of increased mobility, the drain current is increased, and VTH can be decreased. The activation energy (Ea) is strongly depended on the drain bias and the number of grain boundaries. is decreased, caused by the large drain bias and/or smaller number of grain boundaries. This decreased Ea can be reduced VTH due to increased the drain current. VTH of p-type poly-Si TFT employing FESPC on the glass substrate is affected by channel length and VDS due to energy barrier lowering effect at the grain boundary by increased lateral electrical field.

We report the discovery of three new star clusters in the halo of the Local Group dwarf irregular galaxy NGC 6822. These clusters were found in the deep images taken with the MegaPrime at the CFHT covering a total field of 2 deg $\times$ 2 deg. The most remote cluster is found to be located as far as 79 arcmin away from the center of NGC 6822. This distance is several times larger than the size of the region in NGC 6822 where star clusters were previously found. Morphological structures of the clusters and color-magnitude diagrams of the resolved stars in the clusters show that at least two of these clusters are proabably old globular clusters.

Due to a rapid shrinkage in memory devices, backned of the line process experiences great difficulties, especially Al metallization. Furthermore, there is a continuous demands in low line resistance in order to promote device performances. In this article, Al damascene process is proposed as compared to Al patterning process, which suffers from inherent pattering issue at a fine pitch under 70nm. The most difficulties in the development of Al damascene process were to form a stable and void free Al in fine trench and to obtain scratch and corrosions free Al surface. In this study, 50nm beyond fill was successfully achieved by “bottom up growth” of CVD Al. For the process, CVD Al by using Methylpyrroridine Alane (MPA) precursor was deposited on a stacked film of CVD TiN and PVD TiN as a wetting layer, which was followed by PVD Al and reflow, then the Al surface was polished with colloidal silica based slurry.

In addition, electrical property of Al scheme and W scheme was compared with damascene pattern, along with which we demonstrated that around 36% decrease in parasitic capacitance is achievable by decrease of metal line height from 3500A to 1000A on simulation test implying that device performance could be enhanced.

Cu/C films were prepared at room temperature under Cu(hfac)2-Ar-H2 atmosphere in order to obtain metallized polymer by using ECR-MOCVD (Electron Cyclotron Resonance Metal Organic Chemical Vapor Deposition) coupled with periodic DC bias system. Room temperature MOCVD was possible when periodic negative voltage was applied on the polymer substrate. The periodic negative voltage induces ions and radicals to have nucleation reaction on the surface of the substrate. Formation of Cu/C films strongly depends on the periodic negative pattern of DC bias and the electric sheet resistance of the films was controlled from 108 to 100ohm/sq ranges by process parameters such as microwave power and magnet current. The increase in microwave power and magnet current brought on copper-rich film formation with low electric resistance. On the other hand carbon-rich films with high sheet electric resistance were prepared with decreased values for process parameters aforementioned.

Ta2O5 films of high reliability and low leakage current density were obtained by low temperature deposition and subsequent high temperature oxygen anneal. At higher temperatures than 410°C, growth was governed by the formation of radicals in gas phase and oxidation on the surface, while at lower temperatures by the dissociation of reactant on the surface of substrates. As a result, the films deposited at lower temperatures had undensified structures, and contained more carbon that might be a leakage current source in Ta2O5 film. During post-deposition heat treatment in 800°C oxidating ambient, carbon was removed away and silicon was diffused from the substrate into the Ta2O5 film efficiently for its as-grown porous structure. After oxygen anneal, low temperature films get denser and are crystallized to mixed phase of orthorhombic and hexagonal Ta2O5, while high temperature films crystallized to orthorhombic single phase. Ta2O5 capacitor with low temperature films showed superior leakage characteristics applicable to sub-half micron memory devices.