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We present and review dopant mapping examples in semiconductor device
structures by electron holography and outline their potential
applications for experimental investigation of two-dimensional (2D)
dopant diffusion on the nanometer scale. We address the technical
challenges of the method when applied to transistor structures with
respect to quantification of the results in terms of the 2D
p–n junction potential and critically review
experimental boundary conditions, accuracy, and potential pitfalls. By
obtaining maps of the inner electrostatic potential before and after
anneals typically used in device processing, we demonstrate how the
“vertical” and “lateral” redistribution of
boron during device fabrication can directly be revealed. Such data can
be compared with the results of process simulation to extract the
fundamental parameters for dopant diffusion in complex device